Sebastien Bourdeauducq
|
7230508e7c
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fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
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2012-03-06 14:18:22 +01:00 |
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Sebastien Bourdeauducq
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2c375e900f
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sim: remove default sockaddr
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2012-03-06 13:58:49 +01:00 |
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Sebastien Bourdeauducq
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8d16fde48c
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fhdl: add simulation functions in fragment
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2012-03-06 13:58:22 +01:00 |
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Sebastien Bourdeauducq
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aac9752558
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sim: basic functionality working
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2012-03-05 20:31:41 +01:00 |
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Sebastien Bourdeauducq
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c4c22c9ca0
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sim: signal writes working
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2012-03-05 15:40:21 +01:00 |
|
Sebastien Bourdeauducq
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9bbec278c6
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sim: cleanups
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2012-03-04 22:56:56 +01:00 |
|
Sebastien Bourdeauducq
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2cd71e4b5e
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sim: signal reads working
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2012-03-04 22:33:03 +01:00 |
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Sebastien Bourdeauducq
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c0b0161ec9
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sim: compile VPI module
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2012-03-04 21:27:02 +01:00 |
|
Sebastien Bourdeauducq
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29859acc34
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sim: two way IPC working
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2012-03-04 19:17:03 +01:00 |
|
Sebastien Bourdeauducq
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8586daf2dd
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sim: IPC module (lacks str/int encoding)
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2012-03-03 18:55:38 +01:00 |
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Sebastien Bourdeauducq
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7f307c54a9
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README: clarify license
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2012-02-29 20:30:08 +01:00 |
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Sebastien Bourdeauducq
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1b8cb5b46c
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bus/dfi: fix multiphase naming
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2012-02-19 17:57:04 +01:00 |
|
Sebastien Bourdeauducq
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d8d4e81b6e
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bank/csrgen: fix RE generation
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2012-02-18 18:56:18 +01:00 |
|
Sebastien Bourdeauducq
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55a265d967
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bank: add RE signal for registers made of fields
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2012-02-17 23:52:06 +01:00 |
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Sebastien Bourdeauducq
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92dfbb92dd
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bus: add interconnect statements function
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2012-02-17 23:51:32 +01:00 |
|
Sebastien Bourdeauducq
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f995e8b92e
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fhdl: check we pass BV to signals
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2012-02-17 23:50:54 +01:00 |
|
Sebastien Bourdeauducq
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a1ad30faab
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fhdl/verilog: properly connect instance inouts
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2012-02-17 11:08:41 +01:00 |
|
Sebastien Bourdeauducq
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ca7056b07f
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fhdl: support forwarding of bidirectional signals from instance ports
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2012-02-16 18:34:32 +01:00 |
|
Sebastien Bourdeauducq
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c08687b9c6
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bus/dfi: filter signals by direction
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2012-02-15 21:48:05 +01:00 |
|
Sebastien Bourdeauducq
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ef7aea0f31
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bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
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2012-02-15 18:23:31 +01:00 |
|
Sebastien Bourdeauducq
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fa9cf3e466
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bus: add DFI
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2012-02-15 18:09:14 +01:00 |
|
Sebastien Bourdeauducq
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91e279ee04
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bank/csrgen: use new bus API
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2012-02-15 16:42:17 +01:00 |
|
Sebastien Bourdeauducq
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af5230c8ee
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bus: fix simple interconnect
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2012-02-15 16:42:05 +01:00 |
|
Sebastien Bourdeauducq
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0493212124
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bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
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2012-02-15 16:30:16 +01:00 |
|
Sebastien Bourdeauducq
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46b1f74e98
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bus/asmibus/hub: forward data and tag_call
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2012-02-14 14:00:17 +01:00 |
|
Sebastien Bourdeauducq
|
0c214b484e
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Use double quotes for all strings
|
2012-02-14 13:12:43 +01:00 |
|
Sebastien Bourdeauducq
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e11d9b9322
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bus/wishbone2asmi: cache hits working
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2012-02-13 23:11:16 +01:00 |
|
Sebastien Bourdeauducq
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1662e1b3bc
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corelogic: support reverse in displacer/chooser
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2012-02-13 23:10:27 +01:00 |
|
Sebastien Bourdeauducq
|
264be80f2d
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Fix syntax errors and other stupid problems
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2012-02-13 22:28:02 +01:00 |
|
Sebastien Bourdeauducq
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8a61d9d121
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bus/csr: Rename a->adr d->dat to be consistent with the other buses
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2012-02-13 21:46:39 +01:00 |
|
Sebastien Bourdeauducq
|
d6da88d11d
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doc: update ASMI description
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2012-02-13 17:23:32 +01:00 |
|
Sebastien Bourdeauducq
|
060426cb59
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bus/wishbone2asmi: set WM, and send 0 when inactive
|
2012-02-13 16:49:43 +01:00 |
|
Sebastien Bourdeauducq
|
cad9d3b960
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bus: Wishbone to ASMI caching bridge (untested)
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2012-02-13 16:29:38 +01:00 |
|
Sebastien Bourdeauducq
|
244bf17db7
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corelogic/misc: displacer + chooser
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2012-02-11 20:57:08 +01:00 |
|
Sebastien Bourdeauducq
|
e10e4360f3
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corelogic/misc/multimux: less confusing variable name
|
2012-02-11 20:56:51 +01:00 |
|
Sebastien Bourdeauducq
|
7894411418
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bus/asmibus: fix typo
|
2012-02-11 20:56:01 +01:00 |
|
Sebastien Bourdeauducq
|
28b0c340af
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corelogic/record: add to_signal convenience function
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2012-02-11 20:55:23 +01:00 |
|
Sebastien Bourdeauducq
|
e62ac1d3a1
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corelogic/misc: contiguous split
|
2012-02-11 11:52:15 +01:00 |
|
Sebastien Bourdeauducq
|
ef436a1ec9
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bus/asmibus: add get_slots, fix get_fragment
|
2012-02-10 17:49:06 +01:00 |
|
Sebastien Bourdeauducq
|
945d655d45
|
bus: ASMI hub (untested)
|
2012-02-10 15:21:04 +01:00 |
|
Sebastien Bourdeauducq
|
c1bff38861
|
doc: update Bank description
|
2012-02-08 19:26:56 +01:00 |
|
Sebastien Bourdeauducq
|
47883675db
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bus/wishbone2csr: truncate WB data
|
2012-02-06 18:43:34 +01:00 |
|
Sebastien Bourdeauducq
|
1eb348c573
|
fhdl: do not attempt slicing non-array signals to keep Verilog happy
|
2012-02-06 18:07:02 +01:00 |
|
Sebastien Bourdeauducq
|
fcd6583cbb
|
bank: event manager
|
2012-02-06 17:39:32 +01:00 |
|
Sebastien Bourdeauducq
|
3a2a0c4dd8
|
bank: support registers larger than the bus word width
|
2012-02-06 16:15:27 +01:00 |
|
Sebastien Bourdeauducq
|
f3ddfffc47
|
bank: refactoring
|
2012-02-06 13:55:50 +01:00 |
|
Sebastien Bourdeauducq
|
1a86f26a66
|
bank/csrgen: use enumerate
|
2012-02-06 11:18:30 +01:00 |
|
Sebastien Bourdeauducq
|
629e771fc0
|
fhdl/structure: binary constant builder
|
2012-02-05 19:32:11 +01:00 |
Sébastien Bourdeauducq
|
504a169afb
|
Merge pull request #2 from larsclausen/master
migen patches
|
2012-02-03 01:25:38 -08:00 |
Lars-Peter Clausen
|
8380318e84
|
Use enumerate(x) instead of zip(range(x), x)
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
|
2012-02-02 21:28:00 +01:00 |