32f4d246f4
Efinic ConstraintManager improve delete method
2021-09-28 18:04:27 +02:00
06ff638f7a
efinix: rgmii: fix, it's in a working state
2021-09-27 10:11:58 +02:00
1ea0797c82
efinix: ifacewriter: fix DRIVE_STRENGTH and REFCLK_FREQ
2021-09-27 10:11:00 +02:00
179a8018b3
efinix: RGMII phy should be operational (no tested)
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PLL infrastructure should be complete now.
We can also use DDIO input and outputs.
However, there is problem (bug) during P&R:
ERROR(1): [Line 52] Block auto_eth_tx_delayed_clk is
an output pad but sub-block 1 is not an output pad location.
Inderface Designer validation doesn't report any problem.
I have a test project with the same configuration (I compared
the reports for blocks configuration) and it works.
2021-09-23 17:21:17 +02:00
109dbd1d62
efinity: small fixes
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- do not include *.vh files in project,
- add self.options to class EfinityToolchain
- remove unconditional call to self.ifacewriter.add_ddr_xml
2021-09-22 09:53:27 +02:00
b24475b07d
Add an hacked no we memory for Efinix
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Efinity synthesizer cannot infer RAM blocks with write enable.
In order to workaround this (at least for the Litex SoC intergrated
RAM/ROM) a dirty modified Memory class has been created.
This class needs to be rewrite !
2021-09-22 09:47:51 +02:00
bd71dc663f
efinix: more DDR work, still WIP
2021-09-21 14:23:36 +02:00
b765bdf34e
efinix: pll: allow output name to be changed
2021-09-21 14:23:00 +02:00
7a5f5a3682
efinix: remove redundant param in _build_xml
2021-09-21 14:22:17 +02:00
24a920f2d1
efinix: add preliminary DDR support (WIP)
2021-09-21 10:58:54 +02:00
b9e99f576c
efinix: use proper xml to create project file
2021-09-20 13:35:45 +02:00
efebefecea
efinix: add PLL reset and locked pins
2021-09-20 10:42:27 +02:00
a026dd8946
efinix: add AsyncResetSynchronizer
2021-09-20 10:41:59 +02:00
08be77caaf
efinix: ifacewriter, enable design generation
2021-09-20 10:41:00 +02:00
106b1f29a7
efinix: fix programmer load_bitstream
2021-09-20 08:42:27 +02:00
9b6ae2ff03
efinix: support PLL, add dbparser and ifacewriter
2021-09-20 07:56:53 +02:00
0278d3eee8
generic_platform: add a method to delete a constraint
2021-09-20 07:51:26 +02:00
000aabf85b
Initial Efinix Trion support
2021-09-17 09:29:53 +02:00
7f8e2e39f3
cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes.
2021-09-16 18:56:05 +02:00
beb7cc691d
CHANGES: Do 2021.08 release.
2021-09-15 15:05:47 +02:00
343d88e837
setup.py: Expose litex_contributors tool.
2021-09-15 14:38:45 +02:00
05b960d09b
CHANGES: Update.
2021-09-15 12:08:30 +02:00
02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll
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Fix premature selection of full PLL config with no feedback
2021-09-15 08:52:59 +02:00
91ec6e0da8
clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond
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Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs. Emit the same attributes that Diamond's PLL tool does.
2021-09-15 00:07:43 -05:00
6733a3e3e6
clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search
2021-09-15 00:07:43 -05:00
88d302d4db
soc/alloc_region: Ensure allocated Region is aligned on size.
2021-09-14 18:08:07 +02:00
694878a35a
integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints.
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Some boards require specific constraints, so disable them in this case and put constraints in the target file.
2021-09-13 19:32:50 +02:00
cb7b0f44cf
tools/litex_sim: Fix mem_map.
2021-09-13 11:33:16 +02:00
e0e9311ceb
interconnect/wishbone: Specify Wishbone version ( #999 ).
2021-09-08 17:33:01 +02:00
6c2bc02323
build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names.
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This makes it similar to add_platform_command and add more flexibility to constraint the design.
2021-09-08 16:14:58 +02:00
0222697f21
liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size.
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On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.
This will be less accurate but will still provide representative results which
is the aim of this test.
2021-09-08 09:10:21 +02:00
10c4523c32
soc/add_spi_flash: Add rate parameter to select 1:1 SDR or 1:2 DDR PHY.
2021-09-07 15:09:05 +02:00
575af6fc60
litespi/integration: Review/Cleanup #1024 .
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Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
2021-09-07 14:36:13 +02:00
aff2aefa72
Merge pull request #1024 from antmicro/litespi_refactor
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litex: adding litespi to simulation, making litespi compatible with new implementation
2021-09-07 13:17:40 +02:00
bdd4717daa
Merge pull request #1028 from wuhanstudio/fix-syntax-error
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fix: missing colon syntax error
2021-09-07 13:00:48 +02:00
5d9880888c
fix: missing colon syntax error
2021-09-07 11:21:41 +01:00
a6f9ac58bb
build/sim/common: Review/Cleanup #1021 for consistency with other backends.
2021-09-07 09:44:43 +02:00
2b700057b7
Merge pull request #1021 from antmicro/ddr_sim
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litex: Enable simulation of DDR IO by adding oddr/iddr/ddrtristate simulation models.
2021-09-07 09:38:14 +02:00
7c50f52a57
tools/litex_sim: Improve RAM/SDRAM integration and make closer to LiteX-Boards targets.
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litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
2021-09-07 09:27:51 +02:00
1598b5958d
Merge pull request #1017 from asadaleem-rs/master
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customize main ram size from command line argument
2021-09-07 09:15:55 +02:00
e257d91d46
cpu/vexriscv: Review/Cleanup #1022 .
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Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
2021-09-07 09:04:47 +02:00
6b792dce54
Merge pull request #1022 from tcal-x/vex-dcache
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Restructure config flags for dcache/icache presence in Vex.
2021-09-07 08:46:03 +02:00
bafe32dd13
Merge pull request #1020 from shenki/binutils-fixes
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Binutils fixes
2021-09-06 17:16:56 -07:00
ad0fcc22e6
litex: adding legacy mode for litespi
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Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
2021-09-03 09:42:41 +02:00
fa5fd765a4
interconnect/packet: Add dummy to omit list, fixes #1018 .
2021-09-02 18:02:16 +02:00
7bd06d178f
cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input on PLL_ADV).
2021-09-02 15:12:16 +02:00
3cf6126663
litex: adding explicit clk signal to ODDR/IDDR models in DDRTristate
2021-09-02 14:33:16 +02:00
25e0153dd5
litex_sim: use flash model in simulation
2021-09-02 14:33:16 +02:00
837de615e6
liblitespi: adjusting code to oddr/iddr litespi implementation
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Changing litespi registers configuration to be compatible
with a new implementation.
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
2021-09-02 14:33:11 +02:00
0c91bb7b96
litex_sim: adding spi-flash option to simulation
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Signed-off-by: Paweł Sagan <psagan@antmicro.com>
2021-09-02 14:22:34 +02:00
Franck Jullien
Florent Kermarrec
George Hilliard
wuhanstudio
Tim Ansell
Pawel Sagan
Piotr Binkowski