37e463da9a
fix rle when used with subsampler
2015-02-19 11:34:20 +01:00
e495e2f537
driver/la: add samplerate computation (required by sigrok export)
2015-02-19 11:16:32 +01:00
8e0553670a
remove limitation on debug tuple definition
2015-02-19 10:52:57 +01:00
5f19955825
rle: expose length parameter to user, add assertion on dw to encode counter and automatically increase dw in rle mode
2015-02-19 10:42:13 +01:00
5fb6beb473
enable RLE only in POST_HIT_RECORDING state (to ensure programmed offset is respected)
2015-02-19 10:26:34 +01:00
788652c6f8
simplify RLE
2015-02-19 01:43:04 +01:00
87f29a307a
fix typo
2015-02-18 23:35:50 +01:00
3680b48216
dump/sigrok: fix against real dumps, now able to import and export
2015-02-18 21:45:36 +01:00
6bfd5ce1d8
split host files since we now have more drivers/dumps supported
2015-02-18 16:49:38 +01:00
2f6465d439
add sigrok import (to check export against it)
2015-02-18 15:23:04 +01:00
130212039e
continue sigrok export (should almost work)
2015-02-18 11:59:35 +01:00
cd43163d9d
add sigrok export skeleton (wip)
2015-02-18 00:44:33 +01:00
5830575797
logo : add powered by Migen
2015-02-17 23:14:21 +01:00
a5416fa864
host: add Etherbone driver
2015-02-17 01:09:53 +01:00
b64dba7a81
update download instructions
2015-02-12 22:03:04 +01:00
04f7fbd7e2
simplify litescope export with do_exit call and remove automatic clean
2015-02-12 21:15:51 +01:00
989cca24bc
uart2wb: copy UARTTX/UARTRX from MiSoC to avoid dependency
2015-02-02 14:23:01 +01:00
f65848ca92
doc : add link to generated html/pdf
2015-01-28 19:59:49 +01:00
615d7da703
README: fix tabs
2015-01-28 15:55:52 +01:00
9d6a3e7f2a
doc: add skeleton
2015-01-27 21:35:58 +01:00
0c907e5afa
fill building parameters
2015-01-27 20:24:14 +01:00
7f9174f83d
add storage qualifier
2015-01-27 20:14:07 +01:00
fc96b20225
add optional subsampler
2015-01-27 19:58:02 +01:00
70d7152cda
core/storage: split LiteScopeRecorder in LiteScopeRecorderUnit and LiteScopeRecorder
2015-01-27 11:34:59 +01:00
64d18796e0
change CSR class names (do not expose XXYYCSR to user)
2015-01-25 21:34:13 +01:00
a3dae5fc5c
host/driver: simplify
2015-01-25 16:13:06 +01:00
4472dac603
simplify code and use Sink/Source instead of records
2015-01-25 15:58:00 +01:00
6f7d85b95c
host: remove cpuif (we use the one from MiSoC) and some clean up
2015-01-23 16:45:04 +01:00
9a3e9f86cf
simplify LiteScopeLA export (use vns from platform on atexit)
2015-01-23 10:07:58 +01:00
261469814f
add hack to generate verilog with AsyncResetSynchronizer (FIXME)
2015-01-23 03:18:25 +01:00
fb7864c2b9
add missings __init__.py
2015-01-23 01:14:35 +01:00
d45991d6eb
fix README
2015-01-23 01:07:51 +01:00
ea48f44b90
add LiteScopeLA example
2015-01-23 00:46:24 +01:00
5c40ff02cb
add LiteScopeIO example
2015-01-23 00:15:42 +01:00
f35f93a7c5
start refactoring and change name to LiteScope
2015-01-23 00:02:53 +01:00
609f8f9abb
revert submodules/specials/clock_domains syntax
2015-01-22 14:00:50 +01:00
fadac0cf83
drivers: fix mask generation when using cond
2015-01-16 23:50:33 +01:00
8f14f67ea6
simplify UART2Wishbone and add timeout
2015-01-14 18:10:37 +01:00
54597f1bfc
use new submodules/specials/clock_domains automatic collection
2015-01-14 13:55:18 +01:00
834e9b99be
host/drivers: add possibility to pass cond dict to ease trigger pattern generation
2014-12-23 20:53:05 +01:00
8c5c32751e
add input pipe stage option
2014-10-28 20:53:26 +01:00
d860813dec
use new direct access on endpoints
2014-10-16 17:57:30 +02:00
9649b1497c
uart2wishbone: fix missing payload.d
2014-10-16 09:37:43 +02:00
2319ee0ab7
uart2wishbone: always use payload.d and not .d
2014-10-15 12:13:22 +02:00
027ddc65ca
fill __init__.py to simplify imports
2014-10-10 17:24:36 +02:00
bf95ea6c1c
mila: simplify usage
2014-10-10 16:17:12 +02:00
d0c9838dca
uart2wishbone: share UARTRX and UARTTX with MiSoC
2014-10-10 15:15:58 +02:00
ba30a01830
mila: fixes when used without RLE
2014-10-06 12:30:06 +02:00
f72f11f7b4
mila: add clk_domain support
...
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.
future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
7043e6a5f3
mila: simplify export
2014-10-01 10:06:59 +02:00
Florent Kermarrec