Sebastien Bourdeauducq
|
ed27783a53
|
fhdl: arrays (TODO: use correct BV for intermediate signals)
|
2012-07-09 15:16:38 +02:00 |
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
Sebastien Bourdeauducq
|
6a52e44d09
|
fhdl: support len() on signals
|
2012-04-08 18:06:22 +02:00 |
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
Sebastien Bourdeauducq
|
5c0cc6292c
|
fhdl: export log2_int
|
2012-03-14 12:19:42 +01:00 |
Sebastien Bourdeauducq
|
bfcd4e636b
|
fhdl: handle negative constants correctly
|
2012-03-08 20:49:24 +01:00 |
Sebastien Bourdeauducq
|
98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
|
2012-03-06 19:43:59 +01:00 |
Sebastien Bourdeauducq
|
8160ced2e9
|
sim: memory access
|
2012-03-06 19:29:39 +01:00 |
Sebastien Bourdeauducq
|
db8f8bf2e3
|
fhdl: register memory objects with namespace
|
2012-03-06 18:33:44 +01:00 |
Sebastien Bourdeauducq
|
90184b22d2
|
fhdl/verilog: fix signed constant conversion
|
2012-03-06 16:45:44 +01:00 |
Sebastien Bourdeauducq
|
7230508e7c
|
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
|
2012-03-06 14:18:22 +01:00 |
Sebastien Bourdeauducq
|
8d16fde48c
|
fhdl: add simulation functions in fragment
|
2012-03-06 13:58:22 +01:00 |
Sebastien Bourdeauducq
|
f995e8b92e
|
fhdl: check we pass BV to signals
|
2012-02-17 23:50:54 +01:00 |
Sebastien Bourdeauducq
|
a1ad30faab
|
fhdl/verilog: properly connect instance inouts
|
2012-02-17 11:08:41 +01:00 |
Sebastien Bourdeauducq
|
ca7056b07f
|
fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
Sebastien Bourdeauducq
|
1eb348c573
|
fhdl: do not attempt slicing non-array signals to keep Verilog happy
|
2012-02-06 18:07:02 +01:00 |
Sebastien Bourdeauducq
|
629e771fc0
|
fhdl/structure: binary constant builder
|
2012-02-05 19:32:11 +01:00 |
Lars-Peter Clausen
|
2b3f00cbc1
|
fhdl/namer: Add support for STORE_DEREF opcode
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
|
2012-02-02 21:15:10 +01:00 |
Sebastien Bourdeauducq
|
6a9b59786b
|
fhdl/namer: extract variable names with bytecode inspection
|
2012-01-28 23:17:44 +01:00 |
Sebastien Bourdeauducq
|
5c2df45577
|
fhdl: do not prefix instance signal names
|
2012-01-28 11:39:28 +01:00 |
Sebastien Bourdeauducq
|
685b5eb08f
|
fhdl: support memory read enable
|
2012-01-27 21:39:23 +01:00 |
Sebastien Bourdeauducq
|
0cc7e2ac1e
|
fhdl: make WRITE_FIRST default
|
2012-01-27 21:35:58 +01:00 |
Sebastien Bourdeauducq
|
5405a83ff9
|
fhdl: memories working
|
2012-01-27 20:22:17 +01:00 |
Sebastien Bourdeauducq
|
a5bd111370
|
fhdl/verilog: clean up signal classification and support memory descriptions
|
2012-01-27 16:54:48 +01:00 |
Sebastien Bourdeauducq
|
6b1d775e9f
|
fhdl/structure: memory description
|
2012-01-27 16:53:34 +01:00 |
Sebastien Bourdeauducq
|
d3d5b481fe
|
Include fragment pads in pre-naming dictionary
|
2012-01-20 22:59:40 +01:00 |
Sebastien Bourdeauducq
|
039c6d8eb4
|
namer/trace_back: behave on None code_context
|
2012-01-20 22:52:50 +01:00 |
Sebastien Bourdeauducq
|
e9be3241f6
|
Fix instance support
|
2012-01-20 22:36:17 +01:00 |
Sebastien Bourdeauducq
|
e4f531a739
|
Include unused I/Os in pre-naming dictionary and register signals with name_override
|
2012-01-20 22:20:32 +01:00 |
Sebastien Bourdeauducq
|
904d14d4cf
|
Remove NoContext
|
2012-01-20 22:15:44 +01:00 |
Sebastien Bourdeauducq
|
05b20d4987
|
Only include context prefix when necessary
|
2012-01-19 19:25:04 +01:00 |
Sebastien Bourdeauducq
|
fc473e31eb
|
Fix disjoint namespace test
|
2012-01-19 19:24:43 +01:00 |
Sebastien Bourdeauducq
|
00d3eb7989
|
Always include last step in names
|
2012-01-19 18:42:43 +01:00 |
Sebastien Bourdeauducq
|
4eac60d181
|
New naming system: second attempt
|
2012-01-19 18:25:25 +01:00 |
Sebastien Bourdeauducq
|
bdde97f5fd
|
New naming system beginning to work
|
2012-01-16 18:42:55 +01:00 |
Sebastien Bourdeauducq
|
ab8e08a2ed
|
fhdl: new naming system (broken)
|
2012-01-16 18:09:52 +01:00 |
Sebastien Bourdeauducq
|
aa8b8da684
|
fhdl: allow None statements
|
2012-01-15 17:45:54 +01:00 |
Sebastien Bourdeauducq
|
3c7161cc34
|
flow: saner endpoint management
|
2012-01-15 15:09:44 +01:00 |
Sebastien Bourdeauducq
|
b06e70d849
|
corelogic: FSM
|
2012-01-09 16:28:48 +01:00 |
Sebastien Bourdeauducq
|
34c69db14a
|
endpoint: add _i/_o suffix on signal names
|
2012-01-07 21:21:46 +01:00 |
Sebastien Bourdeauducq
|
cdd9977a40
|
fhdl: better signal naming heuristic
|
2012-01-07 15:30:14 +01:00 |
Sebastien Bourdeauducq
|
b6763c28ea
|
constant: equality
|
2012-01-07 12:29:47 +01:00 |
Sebastien Bourdeauducq
|
7b395b565e
|
verilog: split comb block, use assign statements
|
2012-01-07 12:19:06 +01:00 |
Sebastien Bourdeauducq
|
f209bf6b33
|
convtools -> tools
|
2012-01-07 00:39:28 +01:00 |
Sebastien Bourdeauducq
|
3c1dada9cf
|
record: compatibility check
|
2012-01-06 23:00:23 +01:00 |
Sebastien Bourdeauducq
|
d7a3bed44c
|
Signal repr
|
2012-01-06 11:20:33 +01:00 |
Sebastien Bourdeauducq
|
9366a226bb
|
Convert -> convert
|
2012-01-05 19:27:33 +01:00 |
Sebastien Bourdeauducq
|
76db20cd9f
|
fhdl: encapsulate replicated constants
|
2011-12-23 00:35:13 +01:00 |
Sebastien Bourdeauducq
|
8a394f9159
|
verilog: comb reset
|
2011-12-22 00:04:53 +01:00 |
Sebastien Bourdeauducq
|
4d6be55e9f
|
verilog: break down Convert function
|
2011-12-21 23:08:50 +01:00 |
Sebastien Bourdeauducq
|
26e0b817e8
|
verilog: ignore variable property in combinatorial block
|
2011-12-21 23:00:36 +01:00 |
Sebastien Bourdeauducq
|
7456195775
|
Consistent names
|
2011-12-21 22:57:07 +01:00 |
Sebastien Bourdeauducq
|
4f4d809a4e
|
fhdl: better matching of assignment
|
2011-12-18 21:49:48 +01:00 |
Sebastien Bourdeauducq
|
dd42b2daff
|
fhdl: also take into account object attributes in _make_signal_name. Get rid of declare_signal
|
2011-12-18 21:47:29 +01:00 |
Sebastien Bourdeauducq
|
41e2430e2b
|
fhdl: automatic signal name from assignment
|
2011-12-18 21:26:51 +01:00 |
Sebastien Bourdeauducq
|
d21e095397
|
fhdl: fix series of if/elif/else
|
2011-12-17 20:31:42 +01:00 |
Sebastien Bourdeauducq
|
6f8a6db40a
|
verilog: get the simulator to run the combinatorial process at the beginning
|
2011-12-17 15:20:22 +01:00 |
Sebastien Bourdeauducq
|
ec47394012
|
verilog: support for float parameters in instances
|
2011-12-17 14:59:27 +01:00 |
Sebastien Bourdeauducq
|
ee6ca729a2
|
verilog: user-definable reset and clock
|
2011-12-16 22:25:05 +01:00 |
Sebastien Bourdeauducq
|
c7b9dfc203
|
fhdl: simpler syntax
|
2011-12-16 21:30:14 +01:00 |
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
Sebastien Bourdeauducq
|
c840848dba
|
verilog: use blocking assignment in combinatorial process
|
2011-12-13 14:09:12 +01:00 |
Sebastien Bourdeauducq
|
a72faaecdd
|
fhdl: allow a namespace to be specified for Verilog conversion
|
2011-12-13 00:24:40 +01:00 |
Sebastien Bourdeauducq
|
eee6980a36
|
fhdl: support Constant parameters for Verilog conversion
|
2011-12-11 20:17:51 +01:00 |
Sebastien Bourdeauducq
|
dafef5d744
|
fhdl: fix list references (thanks Lars)
|
2011-12-11 20:17:29 +01:00 |
Sebastien Bourdeauducq
|
019ef16db4
|
fhdl: remove broken fragment iadd
|
2011-12-11 01:10:59 +01:00 |
Sebastien Bourdeauducq
|
b00581616e
|
convtools: insert reset on variables
|
2011-12-11 01:10:37 +01:00 |
Sebastien Bourdeauducq
|
d3127fd5d8
|
autofragment: remove debug
|
2011-12-10 20:48:23 +01:00 |
Sebastien Bourdeauducq
|
44f44b8a05
|
fhdl: autofragment
|
2011-12-10 20:47:21 +01:00 |
Sebastien Bourdeauducq
|
4b15a84505
|
fhdl: fix += for empty fragment
|
2011-12-10 20:47:06 +01:00 |
Sebastien Bourdeauducq
|
a49ecc4331
|
fhdl: pad support in fragments
|
2011-12-10 20:25:24 +01:00 |
Sebastien Bourdeauducq
|
fa63cc1ec8
|
fhdl: replication support
|
2011-12-09 13:11:34 +01:00 |
Sebastien Bourdeauducq
|
b0c5b74c22
|
verilog: handle default in case statements
|
2011-12-08 23:04:20 +01:00 |
Sebastien Bourdeauducq
|
512655c108
|
fhdl: improve automatic signal naming
|
2011-12-08 21:28:20 +01:00 |
Sebastien Bourdeauducq
|
84eb964adc
|
fhdl: support negation operator
|
2011-12-08 21:15:44 +01:00 |
Sebastien Bourdeauducq
|
bf021efa2b
|
verilog: fix unary operator conversion
|
2011-12-08 21:15:24 +01:00 |
Sebastien Bourdeauducq
|
ed05ec5f6a
|
instances: signal override
|
2011-12-08 18:56:14 +01:00 |
Sebastien Bourdeauducq
|
a6b86168ce
|
Simple bus base class
|
2011-12-08 18:47:32 +01:00 |
Sebastien Bourdeauducq
|
1b637cea61
|
Instance support
|
2011-12-08 16:35:32 +01:00 |
Sebastien Bourdeauducq
|
fab02f84cb
|
fhdl: fix implicit slice index
|
2011-12-07 22:21:30 +01:00 |
Sebastien Bourdeauducq
|
82f77180d5
|
fhdl: cleanup value bv
|
2011-12-07 22:21:10 +01:00 |
Sebastien Bourdeauducq
|
0e8d894a35
|
Variable conversion
|
2011-12-05 22:00:06 +01:00 |
Sebastien Bourdeauducq
|
4340680704
|
Cleanup
|
2011-12-05 19:25:32 +01:00 |
Sebastien Bourdeauducq
|
ec51f09c98
|
Case support + register bank generator
|
2011-12-05 17:43:56 +01:00 |
Sebastien Bourdeauducq
|
e099f4d52f
|
Reset insertion
|
2011-12-04 22:41:50 +01:00 |
Sebastien Bourdeauducq
|
cd8544c758
|
Verilog generator
|
2011-12-04 22:26:32 +01:00 |
Sebastien Bourdeauducq
|
499b95a519
|
Initial import, FHDL basic structure, divider example
|
2011-12-04 16:44:38 +01:00 |