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3721 commits

Author SHA1 Message Date
Franck Jullien
438bb0b570 sim: allow custom modules to be in custom path 
If a project needs a custom verilator module, it can now
specifies the path where the module's directory is.

SimPlatform can now look for extra modules:

    builder.build(
        extra_mods = ["mymodule1", "mymodule2"],
        extra_mods_path = os.path.abspath(os.getcwd()) + "/modules",
        sim_config=sim_config
    )

Modules must be subdirectories of extra_mods_path:

.
├── modules
│   ├── mymodule1
│   ├── mymodule2
│   ├── ...
 2022-01-09 21:15:11 +01:00
Franck Jullien
330144021b soc: raise an error if adding a SoCRegion with incoherent cache configuration 2022-01-06 09:55:53 +01:00
Franck Jullien
2174a9219b efinix: add gpio MIPI_CLKIN to ifacewriter 2021-12-21 12:39:22 +01:00
enjoy-digital
55268af279
Merge pull request #1129 from gsomlo/gls-json2dts-update 
clock, mmc updates for json2dts_linux
 2021-12-20 21:27:06 +01:00
enjoy-digital
9e44e856cc
Merge pull request #1137 from trabucayre/zynq_tcl_preset 
zynq7000: add TCL preset support
 2021-12-20 21:25:40 +01:00
enjoy-digital
58f9bce567
Merge pull request #1135 from fjullien/bios_add_variable_size_mem_write 
bios: add write size option to cmd mem_write
 2021-12-20 21:23:16 +01:00
Gwenhael Goavec-Merou
14e0aeb92a zynq7000: add TCL preset support 2021-12-20 16:54:18 +01:00
Franck Jullien
f4dab5adac bios: add write size option to cmd mem_write 2021-12-17 20:45:41 +01:00
Franck Jullien
ca67ed8c13 efinix: check SLEWRATE property when adding a 'normal' GPIO 2021-12-17 13:52:05 +01:00
Franck Jullien
df20ea5aa8 efinix: when a GPIO block is added, also add pin properties 2021-12-17 13:52:05 +01:00
Franck Jullien
df34b3ae6a efinix: supports for EfinixTristateImpl with nbits > 1 2021-12-17 13:51:56 +01:00
Florent Kermarrec
a6ed4c5c09 cores/prbs: Change wrap parameter to with_errors_saturation (opposite) and disable saturation by default. 2021-12-14 09:41:17 +01:00
enjoy-digital
fda682a4a6
Merge pull request #1132 from smunaut/prbs 
cores/prbs: Add a 'wrap' option to PRBSRX
 2021-12-14 08:17:08 +01:00
Sylvain Munaut
477e51849a cores/prbs: Add a 'wrap' option to PRBSRX 
If enabled, then the error count wraps around when it
reaches the limit of the 32b counter instead of saturating
to a max value.

Software can then detect the wrap and act accordingly.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2021-12-13 19:46:06 +01:00
Franck Jullien
40c001d522 check calculated PLL frequencies against user's values 2021-12-13 14:47:57 +01:00
Franck Jullien
eafee9dac5 efinix: add Titanium PLL support 2021-12-13 14:47:49 +01:00
Franck Jullien
148d124d03 efinix: get family name from device name 2021-12-13 14:36:54 +01:00
Franck Jullien
f37188c358 efinix: add more valid IOStandard 2021-12-13 14:34:08 +01:00
Franck Jullien
12e5443489 efinix: fix efxpt:single_conn parsing 
Sometimes instance can be this form:

<efxpt:single_conn ... instance="GPIOT_PN_16.lvttl1,...

This patch handle this case
 2021-12-13 14:31:34 +01:00
Florent Kermarrec
92f5a9f0e6 soc/cores/led/WS2812: Add Bus Mastering capability. 
Useful on small FPGAs to reduce resource usage: When enabling bus mastering,
the core is able to automatically read led values from the bus and can then
avoid the internal memory. This is particularly useful when reading values
from SPI Flash with a small "Player" core just updating the base address.
 2021-12-12 15:18:24 +01:00
Gabriel Somlo
d108d2ad3d tools/litex_json2dts_linux.py: update mmc node 
Add `reg-names` property, which facilitates cleaner probing
for the upstream Linux device driver. Also, add a reference
to the LiteX sys_clk, also for the benefit of the upstream
driver, which can't rely on the CPU frequency matching sys_clk.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-12-10 11:05:58 -05:00
Gabriel Somlo
b4fb3ea981 tools/litex_json2dts_linux.py: update clock specification 
Remove `bus-frequency` property from `soc` node. Instead,
create a separate `clocks` section containing a node to
represent the LiteX sys_clk, which may be referenced from
other peripherals if needed.

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2021-12-10 11:02:35 -05:00
Greg Davill
416886c723 software.fatfs: Align fatfs sector buffers 2021-12-10 17:27:26 +10:30
Florent Kermarrec
230ba5f7ba cpu/gowin_emcu: Minor cosmetic cleanups, add copyright. 2021-12-09 16:01:41 +01:00
enjoy-digital
7286f95f55
Merge pull request #1125 from fjullien/efinix_add_bank_voltage 
efinix: add io bank voltage configuration
 2021-12-09 14:26:33 +01:00
Ilia Sergachev
db83b38a2a cores/cpu: add initial Gowin EMCU support 2021-12-08 23:51:57 +01:00
Ilia Sergachev
18a1d74cf6 soc/interconnect: add basic ahb support 2021-12-08 23:08:45 +01:00
Franck Jullien
5efb64b80b efinix: add io bank voltage configuration 2021-12-08 18:04:11 +01:00
Florent Kermarrec
9482cbc85d soc/add_pcie: Expose more DMA parameters. 2021-12-08 08:21:09 +01:00
enjoy-digital
d3b493d4e8
Merge pull request #1124 from tcal-x/cfu-finalize 
Defer adding the CFU instance until cpu.do_finalize().
 2021-12-07 18:34:09 +01:00
Tim Callahan
85a3b00d1f Defer adding CFU instance until cpu.do_finalize(). 
Signed-off-by: Tim Callahan <tcal@google.com>
 2021-12-07 00:09:59 -08:00
Ray Molenkamp
235e55c9af build/altera: fix rbf generation on windows 
Testing for a file existing is slightly different
between bash and .bat files which caused the batch
file to error out.
 2021-12-06 09:39:19 -07:00
Greg Davill
4679b86314 soc.intergration.dram: Use nranks in capacity calc 
This ensures that dual ranked memory appears with the correct capacity
 2021-12-05 15:34:24 +10:30
Florent Kermarrec
d9c44c46ab cores/clock/gowin_gw1n: Add back GW1NR support. 2021-12-02 18:22:42 +01:00
enjoy-digital
e6f316d0f4
Merge pull request #1115 from sergachev/master 
Improve Gowin clock primitive support
 2021-12-02 09:13:31 +01:00
Andrew Dennison
b8710e44b8 build/efinix: Fix VHDL support. 2021-12-01 08:32:49 +01:00
enjoy-digital
c5cd2e55e6
Merge pull request #1116 from lschuermann/dev/sim-remove-ifg-debug 
litex_sim/xgmii: remove IFG SUFFICIENT debug message
 2021-11-30 16:07:49 +01:00
Florent Kermarrec
16a43e983e cores/gpio/GPIOTristate: Use Record.flatten() instead of Record.raw_bits(). 
Fix verilog syntax error.
 2021-11-30 15:48:34 +01:00
Florent Kermarrec
9036050364 cores/gpio/GPIOTristate: Allow passing platform resource with subsignals directly. 2021-11-30 15:32:48 +01:00
Leon Schuermann
c18635ad19 litex_sim/xgmii: remove IFG SUFFICIENT debug message 
Removes a leftover debug message for validating correct XGMII IFG DIC
behavior. Useful for development, but gets annoying quickly while
running the simulation.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-11-30 14:19:12 +01:00
Florent Kermarrec
aebef65932 build/generic_platform/add_source: Tranform filename to absolute path earlier to catch duplications when relative/absolute paths are used in design. 2021-11-29 14:17:58 +01:00
enjoy-digital
f2319d39d4
Merge pull request #1114 from andykitchen/femtorv-reset-fix 
fix FemtoRV reset signal
 2021-11-29 08:07:13 +01:00
Joel Stanley
24ec49db2e microwatt: Use Xilinx multiplier 
Use the technology specific multiplier implementation when building for a
Xilinx platform.

This isn't understood by yosys so we can't use it when yosys is used for
synthesis.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-11-29 15:30:19 +10:30
Andy Kitchen
2562ae5f63 fix FemtoRV reset signal 2021-11-28 22:35:46 +11:00
Ilia Sergachev
f743dd3873 cores/clock/gowin: merge GW1NS PLL support into GW1N; add more details to PLL frequency ranges 2021-11-28 11:59:36 +01:00
Florent Kermarrec
85d6cb4b8d build/anlogic: Minor cosmetic cleanups. 2021-11-23 19:12:31 +01:00
Miodrag Milanovic
fac2b2a9fb Add initial support for Anlogic devices 2021-11-22 19:08:58 +01:00
Florent Kermarrec
aecfbc0609 cpu/femtorv/core: Fix standard variant march. 2021-11-22 09:34:38 +01:00
Florent Kermarrec
440ef4e2b5 cpu/femtorv/core: Fix petitbateau's march (rv32imfc). 2021-11-22 09:12:45 +01:00
Florent Kermarrec
a96304e287 cpu/femtorv/core: Generate gcc_flags from GCC_FLAGS/Variants. 2021-11-22 09:10:04 +01:00