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Author SHA1 Message Date
enjoy-digital
3ba5d6f187
Merge pull request #1093 from cr1901/ccache 
Add option in Makefile for (s)ccache support.
 2021-10-30 22:49:32 +02:00
Florent Kermarrec
28c8436e01 fhdl/memory/write: Avoid slicing data when memory.width == port.we_granularity. 2021-10-30 22:42:55 +02:00
William D. Jones
86ef4e95a5 Add option in Makefile for (s)ccache support. 2021-10-29 21:04:05 -04:00
Florent Kermarrec
942e50b992 fhdl/verilog: Improve code presentation. 
- Add a LiteX Header/Trailer.
- Add _print_signal function.
- Add more infos to the Header.
- Add separators between blocks of code.
- Align Wire/Reg definition.
 2021-10-28 20:14:35 +02:00
Florent Kermarrec
08a9392c54 fhdl/memory: Simplify Read Logic. 2021-10-28 14:34:52 +02:00
Florent Kermarrec
576bb67332 fhdl/memory: Simplify Write Logic (Avoid specific cases on write granuarity). 2021-10-28 14:19:35 +02:00
Florent Kermarrec
d86cd94c71 efinix/memory: Avoid specific memory_efinix generator by applying FullMemoryWE on the design. 2021-10-28 12:11:40 +02:00
Florent Kermarrec
3d4e45145d fhdl/memory: Simplify logic generation and improve intermediate address/data register naming. 2021-10-28 11:25:53 +02:00
Florent Kermarrec
95e5f20bd8 fhdl/memory: Simplify Write Logic generation when with granularity. 2021-10-28 11:11:09 +02:00
Florent Kermarrec
b6c4f6ae24 fhdl/memory: Add initial Memory description. 
Gives an overview of the generated Verilog Memory, will be useful for debug/improve inference.
 2021-10-28 10:51:58 +02:00
Florent Kermarrec
71f8fc7cb5 fhdl/memory: First Cleanup/Re-organization pass. 
- Reorganize a bit (move Memory initialization to Memory declaration block).
- Use f-strings.
- Add separators.
- Add comments.
 2021-10-28 10:07:13 +02:00
Greg Davill
5faddcdb50 soc.jtag.ecp5: Support all ECP5 devices 
- "LFE5UM" devices exclude these without serdes
 2021-10-27 20:36:31 +10:30
Florent Kermarrec
296688b2d8 cores/jtag/ECP5JTAG: Fix LUT4's INIT to create a buffer instead of inverter, thanks @gregdavill. 
Avoid restriction to even number for tck_delay_luts.
 2021-10-27 11:01:09 +02:00
Florent Kermarrec
0b40d78b0d cores/jtag/ECP5JTAG: Delay TCK with LUT4 to avoid sys_clk/jtag_clk relationship and support higher jtag_clk frequencies. 
Tested succesfully on the ButterStick with 75MHz sys_clk/25MHz jtag_clk.

Current tck_delay_luts is abritrary and should probably be adjusted.
 2021-10-26 19:59:02 +02:00
Florent Kermarrec
16af95e424 cores/jtag/ECP5JTAG: Minor cleanup, add Gabriel to copyrights (#797). 2021-10-26 18:07:09 +02:00
enjoy-digital
d4ee5d1399
Merge pull request #1087 from gregdavill/jtag-ecp5 
Add JTAG support on ECP5
 2021-10-26 18:00:50 +02:00
Florent Kermarrec
07b856d01e cores/cpu/mor1kx: Fix gcc_triple (Was duplicated). 2021-10-26 16:06:10 +02:00
Greg Davill
bd65cf6b30 soc.cores.jtag: Add ECP5JTAG 2021-10-26 22:36:23 +10:30
Florent Kermarrec
8c62bb8d2e fhdl/memory_efinix: Add efx to transformed memories to avoid conflicts. 
Fix the crash with the LiteX identifier.
 2021-10-25 19:32:18 +02:00
Florent Kermarrec
7914923d2d soc/build: Avoid no_we mode on RAMs and move specialization of Efinix memories to fhdl. 
Specialization still only support 32-bit RAMs and will still need to be refactored.
 2021-10-25 19:08:09 +02:00
Florent Kermarrec
a3678c1298 build/efinix/ifacewriter: Remove add_ddr_xml (too early to support it). 2021-10-25 18:17:07 +02:00
Florent Kermarrec
0ed3803291 cores/clock/efinix_trion: Switch to excluded_ios and simplify create_clkout. 2021-10-25 18:14:45 +02:00
Florent Kermarrec
fff5895130 build/efinix: Avoid deleting IOs from platform (too complicated), just use an excluded IOs list. 
Also remove generic_platform's delete that was only used for here.
 2021-10-25 18:13:56 +02:00
Florent Kermarrec
5dc377eda1 clock/efinix_trion: Cleanup PLL block, fix reset polarity and always enable it. 2021-10-25 17:49:39 +02:00
Florent Kermarrec
36b26006a4 fhdl/verilog: Only collect IOs when ios set is empty. 2021-10-25 17:17:50 +02:00
Florent Kermarrec
7662ec5531 clock/efinix_trion: Replace ' with ". 2021-10-25 17:11:10 +02:00
Florent Kermarrec
cfc0b1d337 clock/efinix_trion: Remove count (this will have to be correctly implemented). 2021-10-25 17:09:47 +02:00
Florent Kermarrec
8dc727b514 build/efinix/common: Cleanup EfinixTristateImpl. 2021-10-25 15:00:43 +02:00
Florent Kermarrec
ce1660da4d generic_platform/fhdl/verilog: Move IOs collection to fhdl/verilog. 
IOs can be genererated while lowering specials on Efinix FPGAs.
 2021-10-25 14:40:21 +02:00
Florent Kermarrec
0784fd0396 build/efinix/__init__.py: Remove EfinixDDR import. 2021-10-25 12:43:28 +02:00
Florent Kermarrec
c04753bd3a build/efinix: Remove ddr/rgmii/video cores support (will have to be integrated properly in LiteDRAM/LiteEth/LiteX and integrated in LiteX-Boards). 2021-10-25 12:32:30 +02:00
Florent Kermarrec
cab1742cf0 build/efinix: Remove useless () on classes. 2021-10-25 12:23:36 +02:00
Florent Kermarrec
e6f7dbe69b build/efinix/dbparser: Fix syntax error. 2021-10-25 11:36:23 +02:00
enjoy-digital
a083c34e47
Merge pull request #1078 from trabucayre/efinix_pllv1 
efinix: pll v1 (T4/T8) support
 2021-10-25 11:26:46 +02:00
Florent Kermarrec
47b3c9bc08 soc/interconnect/packet: Remove last_be support in LiteX, specialized Packetizer/Depacketizer have been moved to LiteEth to simplify development and avoid eventual regresion on others cores. 
As seen during the last LiteEth developments, last_be data qualifier is not easy to handle correctly and should be replaced by a simpler data qualifier (similar to AXI's tkeep/tstrb). It will
be easier to do so by having a local copy of Packetizer/Depacketizer directly in LiteEth (still with last_be support) and work on the simpler data qualifier in LiteX (and test it on LitePCIe).
 2021-10-25 11:17:36 +02:00
Leon Schuermann
f2a622975a litex_sim/xgmii_ethernet: fix RX frame check sequence generation 
The rewritten XGMII Ethernet module generates proper frame check
sequences (FCS) on Ethernet frames received by the simulation, such
that the unmodified MAC pipeline including CRC checking can be
used. However, the byte order of the generated frame check sequence
has been inverted. This becomes apparent when one specifies that the
CRC should be calculated in the LiteX BIOS.

This fixes the byte order to be correct. The similar GMII Ethernet
module did not contain this mistake.

Fixes: 7b533a032d ("litex_sim: rewrite XGMII verilator...")
Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-10-25 08:57:36 +02:00
Gwenhael Goavec-Merou
3c209c6c1f efinix: pll v1 (T4/T8) support 2021-10-24 17:39:57 +02:00
Florent Kermarrec
8e448592f0 interconnect/packet: Revert old last/ready logic handling (new one breaks test_packet) and comment out test_packet2 tests (does not seems to be working with previous last/ready handling). 2021-10-23 18:21:47 +02:00
Florent Kermarrec
f3f9737697 interconnect/packet: Add FIXME notes. 2021-10-23 17:43:55 +02:00
enjoy-digital
434b3a3654
Merge pull request #1008 from lschuermann/dev/packetizer-last_be-fix 
{Dep,P}acketizer: properly handle last_be wraparound
 2021-10-23 17:33:29 +02:00
enjoy-digital
adc3aecc56
Merge pull request #1074 from navan93/use-ibex-main-repo 
Use ibex main repo
 2021-10-23 17:24:04 +02:00
Florent Kermarrec
68b67af1bd build/efinix/common: Add initial Tristate/SDRTristate support. 2021-10-22 20:02:17 +02:00
Florent Kermarrec
89b66be323 build/efinix/efinity: Fix Slice case on get_pin_location/get_pin_name. 2021-10-22 20:01:31 +02:00
Florent Kermarrec
62c7978cfd fhdl/verilog: Add optional platform parameter and set platform to specials. 
Being able to access the platform when lowering specials is required for Efinity.
 2021-10-22 20:00:27 +02:00
Florent Kermarrec
2a775e1493 efinix/efinity: Remove spi_low_power_mode (Prevents BIOS XiP). 2021-10-22 10:41:42 +02:00
Florent Kermarrec
f7a256bc5b tools/litex_client: Add --length parameter for MMAP read accesses. 2021-10-22 09:07:19 +02:00
enjoy-digital
14c39c0f2b
Merge pull request #1075 from cr1901/sb_io-pin_input 
Set LatticeiCE40SDROutputImpl to `PIN_INPUT` mode.
 2021-10-22 09:05:26 +02:00
William D. Jones
140e4586ab Use PIN_INPUT mode in LatticeiCE40SDROutputImpl because i_INPUT_CLK is not connected. 2021-10-21 12:11:52 -04:00
Florent Kermarrec
6f8fbfb619 soc/add_cpu: Avoid checking variant with CPUNone. 2021-10-21 11:44:45 +02:00
Florent Kermarrec
d16d4917d6 build/openfpgaloader: Allow reuse of programmer for consecutive commands and fix --offset. 
- Avoid appending to self.cmd on each load_bitstream/flash call to allow reused of programmer object.
- Convert address to str.
 2021-10-21 11:25:32 +02:00
Navaneeth Bhardwaj
a7a746473d Fix missing include in ibex 
Change Ibex to use pythondata-cpu-ibex package and also fix the error of missing include by adding the dependency files first to the list of source files. As mentioned in  lowRISC/ibex#1461.
 2021-10-20 18:26:02 +05:30
Navaneeth Bhardwaj
cf2e073b14 Add changes to use Ibex from pythondata-cpu-ibex 2021-10-20 07:28:13 +05:30
Florent Kermarrec
8fa4de5ede cores/video: Interpret CSI Move Up as Clear XY. 2021-10-19 17:24:41 +02:00
Florent Kermarrec
b9545c2276 cpu/ibex: Add local patch to fix missing import. 2021-10-19 15:43:27 +02:00
enjoy-digital
f4bd729d28
Merge pull request #1070 from navan93/ibex-irq-support 
Fix the support for Ibex.
 2021-10-19 15:43:12 +02:00
Florent Kermarrec
78237fffd9 cores/cpu: Avoid complex port types on microwatt_wrapper. 
microwatt_wrapper.vhdl was introduced for this since some toolchains don't
support complex VHDL ports types on verilog instances (ex previous version
of Vivado).
 2021-10-19 15:04:12 +02:00
enjoy-digital
2a97b6a1c1
Merge pull request #1067 from antmicro/fix-microwatt-synthesis 
Fix microwatt synthesis
 2021-10-19 14:43:11 +02:00
Florent Kermarrec
4335e305f7 cpu/mor1kx: Add or1k-linux to gcc_triple. 2021-10-19 14:42:15 +02:00
Andrew Dennison
a043b2536d efinix: abort if scripts fail 
* get obscure downstream errors when the scripts blindly continue
 2021-10-19 12:51:32 +11:00
Andrew Dennison
f426872e0c efinix: read pll names from database 2021-10-19 12:51:32 +11:00
Andrew Dennison
1fd99b366a soc: report System clock to 3dp 2021-10-19 12:51:32 +11:00
Andrew Dennison
0e164bb23c build/generic_platform: include identifier in ValueError 
* show which identifier is incorrectly specified
 2021-10-19 12:49:05 +11:00
Navaneeth
0fbaa51c71 Change to common isr handler 2021-10-19 07:14:36 +05:30
Andrew Dennison
053e540b8a soc/csr: ValueError if write would be truncated in simulation 2021-10-19 10:42:52 +11:00
Andrew Dennison
04e9ffa2b2 soc/csr: Document simulation side effects of read/write 2021-10-19 10:42:52 +11:00
Florent Kermarrec
467c1b9b88 builder: Move Meson check to _check_meson and only do it when using BIOS. 2021-10-18 18:48:47 +02:00
Navaneeth
ef8bab4c11 Add support for Ibex interrupt 
Initial support for a working Ibex interrupt. Tested in Verilator.
 2021-10-18 20:02:05 +05:30
Florent Kermarrec
2a109c3a3e integration/builder: Add Meson install/version check. 2021-10-18 08:41:51 +02:00
navaneeth
c8a83461b4 Add initial changes to add IRQ support 
In the waveform IRQ pending seems to be going high but the call to ISR() doesn't happen.
 2021-10-17 12:32:31 +05:30
navaneeth
b2b0ba66e5 Fix the support for Ibex. 
Take care of the module change in instantiation of Ibex core.
 2021-10-16 16:29:00 +05:30
Gwenhael Goavec-Merou
627363906c efinix: don't hardcode timing model 2021-10-16 07:20:17 +02:00
Florent Kermarrec
306bdcaed8 fhdl/verilog: Fix regression introduced in to_signed function. 2021-10-15 21:46:42 +02:00
Miodrag Milanovic
8692ddfbff Set defaults for efx_pgm pass 2021-10-15 16:40:01 +02:00
Florent Kermarrec
37dd6c1edb fhdl/verilog: Update header. 2021-10-15 15:25:23 +02:00
Florent Kermarrec
3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX). 2021-10-15 15:20:01 +02:00
Florent Kermarrec
fe2998a19c fhdl/verilog: Remove create_clock_domains (not used in LiteX). 2021-10-15 15:12:30 +02:00
Florent Kermarrec
8c3508e7f5 fhdl/verilog: Remove dummy_signal (no longer used). 2021-10-15 15:09:41 +02:00
Florent Kermarrec
f692f50d06 fhdl/verilog: Remove reg_initialization (always enabled in LiteX). 2021-10-15 15:01:41 +02:00
Florent Kermarrec
84e8fd0f9e fhdl/verilog: Add larger separators. 2021-10-15 14:55:46 +02:00
Florent Kermarrec
5a2399b037 fhdl/verilog: Remove display_run (not used in LiteX). 2021-10-15 14:43:42 +02:00
Florent Kermarrec
8aad25ae2b fhdl/verilog: Create _print_cat/_print_replicate, start cleaning up convert. 2021-10-15 14:25:33 +02:00
Florent Kermarrec
2c98ad94b5 fhdl/verilog: Create _print_operator/_print_slice, move code outside _print_expression and cleanup/simplify. 2021-10-15 13:54:06 +02:00
Florent Kermarrec
cdfb8d141a fhdl/verilog: Simplify _print_signal/_print_constant, add comments to _print_expression. 2021-10-15 11:51:39 +02:00
Florent Kermarrec
a18107f795 fhdl/verilog: Give more explict names to print functions. 2021-10-15 11:27:34 +02:00
Florent Kermarrec
86178ed2d9 fhdl/verilog: Update Reserved Keywords (from IEEE 1800-2017) and minor cleanup. 2021-10-15 11:06:31 +02:00
Michal Sieron
5b166b3aa4 Fix microwatt synthesis 
Microwatt uses now 29 bit wishbone addresses, so 3 additional bits for
compatibility are no longer needed.

Rest is minimal set of changes that was needed to make it build.
 2021-10-14 19:57:11 +02:00
Florent Kermarrec
adf30928d4 build/efinix/efinity: Simplify get_pin_direction with direction/name already set to signals when generating the verilog. 2021-10-14 19:12:00 +02:00
Florent Kermarrec
2628140e8a soc_core: Also add "no_we" support to integrated_main_ram (and improve add_ram/add_rom calls). 2021-10-14 10:18:17 +02:00
Florent Kermarrec
8316fbf14b build/efinix/common: Fix EfinixAsyncResetSynchronizerImpl. 
SR_VALUE is set to 0 by default and needs to be set to 1.
 2021-10-13 16:31:47 +02:00
Florent Kermarrec
f0a3fcfefa build/efinix: Improve error message when Efinity toolchain is not found. 2021-10-13 14:41:44 +02:00
Florent Kermarrec
fd354c5759 gen/fhdl/memory: Fix dual clock memory pattern (previous pattern is no longer supported by Yosys), thanks @gregdavill. 
See https://github.com/enjoy-digital/litex/issues/1003.
 2021-10-13 11:33:43 +02:00
Florent Kermarrec
8fbd1b84a4 gen/fhdl: Use a local emit_verilog function for Memory. 
With the various FPGA now supported, being able to generate valid verilog patterns
that will be infered correctly is now complicated.

Use our local version of emit_verilog to be able to specialize more easily the generated
code.

This will also allow use to progressively remplace Migen's Memory.
 2021-10-13 10:58:49 +02:00
Florent Kermarrec
269b84eca4 build/efinix: Move tweaked Memory to build/efinix for now. 2021-10-13 09:51:47 +02:00
Florent Kermarrec
a99b4cac48 build/efinix: Minor initial cleanups. 2021-10-13 09:42:39 +02:00
enjoy-digital
eafa0fe83e
Merge pull request #1066 from fjullien/efinix 
Initial Efinix support.
 2021-10-13 09:17:32 +02:00
Florent Kermarrec
5e3e78f760 soc/add_pcie: Automatically set Endpoint's endianness to PHY's endianness. 2021-10-12 15:46:35 +02:00
enjoy-digital
f93b6b9f27
Merge pull request #1065 from shenki/microwatt-picolibc-family 
microwatt: Fix family property
 2021-10-12 09:08:57 +02:00
Florent Kermarrec
a489dadfbc cpu/CPUNone: Add ethmac to mem_map as temporary build workaround for --cpu-type=None --with-ethernet. 2021-10-12 09:02:48 +02:00
Joel Stanley
79ae6a99ab microwatt: Fix family property 
In commit 061b89beff ("cpu/picolibc: Add family property to CPUs and
directly use it for picolibc.") a family was added for meson cross
compilation, but this doesn't exist, leading to the following warning:

 WARNING: Unknown CPU family powerpc, please report this at https://github.com/mesonbuild/meson/issues/new

Instead use ppc64. While this seems wrong for a ppc64le machine, it
appears to be what meson expects.

Signed-off-by: Joel Stanley <joel@jms.id.au>
 2021-10-12 17:21:09 +10:30
Florent Kermarrec
96cfb44851 soc: Raise custom SoCError Exception and disable traceback/exception since already described. 2021-10-12 08:35:14 +02:00
Chris Osterwood
665665e1cc
Update icestorm.py with u4k device, since Yosys can target it 2021-10-08 15:20:39 -04:00
Florent Kermarrec
db20cb172d cores/video/VideoFrameBuffer: Add missing ClockDomainsRenamer on Converter (thanks @rdolbeau). 
Converter was not running in the right clock domain in ((dram_port.data_width > depth) and clock_faster_than_sys) case.
 2021-10-08 14:33:04 +02:00
Florent Kermarrec
f508b131ea cores/video: Change depth parameter to format (more explicit and we'll maybe want to support other video formats). 2021-10-08 14:28:04 +02:00
enjoy-digital
6d317d0882
Merge pull request #1053 from rdolbeau/fb_rgb565 
Add 16-bits, RGB565 FB support in simple-framebuffer
 2021-10-08 14:15:10 +02:00
Gabriel Somlo
18bd8f3770 cpu/rocket: add dual-core (smp) variants 
- 2-core "linux" (fpu-less) variants with double, quad mem. bus width
 2021-10-06 08:48:27 -04:00
Florent Kermarrec
f03a15820b tools/litex_sim: Remove useless pre_run_callback toolchain attribute. 2021-10-06 09:16:08 +02:00
enjoy-digital
04885a5d77
Merge pull request #1057 from antmicro/rocket-asm-alignment 
cpu/rocket: naturally align data defined in crt0.S
 2021-10-04 17:57:43 +02:00
Florent Kermarrec
99f3498f2d cores/icap/ICAP: Add Register read capability. 
Useful to get some internal status, ex the IDCode or know if the executed bistream
in a multiboot configuration is the operational or fallback one.
 2021-10-04 17:22:57 +02:00
Jakub Piecuch
771897fa37 cpu/rocket: naturally align data defined in crt0.S 
The startup code accesses this data using sd/ld instructions, which
require that the address being accessed is 8-byte aligned.
The .dword asm directive does NOT imply any alignment, so we need
to force it using the .align directive.
 2021-10-04 15:22:13 +02:00
Florent Kermarrec
3504904c09 cores/icap/ICAP: Rewrite using with an FSM instead of Timeline (will be easier to extend). 2021-10-04 15:06:03 +02:00
Florent Kermarrec
9416e30249 test/test_icap: Add IPROG sequence check. 2021-10-04 14:41:38 +02:00
Florent Kermarrec
cb2f2d7021 cores/icap/ICAP: Rewrite using constants and cleanup. 2021-10-04 14:25:40 +02:00
Florent Kermarrec
1f2b143c66 cores/icap: Add Configuration Registers and Commands definition. 2021-10-04 13:35:36 +02:00
Florent Kermarrec
6b3b243bb3 cores/icap: Fix/Update comment. 2021-10-04 11:37:40 +02:00
Florent Kermarrec
cb6861e1c8 build: Add initial/minimal QuickLogic build support. 2021-10-01 11:42:56 +02:00
Gabriel Somlo
d92f10dfb0 64-bit follow-up for picolibc warning fixes 
Providing "uint32_t" to printf's "%ld" results in warnings on 64-bit
builds: use "unsigned long" instead.
 2021-09-30 20:26:40 -04:00
Romain Dolbeau
bf004d48e9 Add 16-bits, RGB565 FB support in simple-framebuffer 2021-09-30 19:40:03 +02:00
Florent Kermarrec
77283d3d8d software: Fix picolibc compilation warnings. 2021-09-30 19:24:58 +02:00
Florent Kermarrec
841732f38f software/liblitesata: Fix compilation with picolibc. 2021-09-30 18:56:01 +02:00
enjoy-digital
7b7fd25d5d
Merge pull request #1054 from niw/fix_disk_read_arg_name 
FIX: arg name is changed.
 2021-09-30 17:44:33 +02:00
Yoshimasa Niwa
abcf5f1d7b FIX: arg name is changed. 2021-09-30 02:56:19 -07:00
Florent Kermarrec
47e4a1b437 tools/litex_term: Avoid staying in safe mode on next upload when previous calibration failed. 2021-09-30 10:11:48 +02:00
Florent Kermarrec
5661480409 tools/litex_term: Add automatic inter-frame delay calibration and --safe mode. 
By default, litex_term will now automatically try to find the best inter-frame delay/payload length
parameters to optimize upload speed. The --safe mode can also be used to disable outstanding frames
(and then wait ack for each frame), it will be slow on regular UARTs (that have high round-trip
latencis) but should always work.
 2021-09-29 18:41:06 +02:00
Florent Kermarrec
80cb53fb04 software/bios/boot: Allow frame reception to time out during serial boot and do some cleanup/add comments. 
Allowing the serial boot to time out during frame reception allows doing test on the Host side to
calibrate the minimum inter-frame delay and maximum payload length.

In the future, we should probably compute the CRC directly during frame reception and do the mempcpy
of frame N during the reception of frame N+1 to avoid these inter-frame constraints.
 2021-09-29 18:33:59 +02:00
Franck Jullien
93c470aecb Efinix: add a local video.py with VideoLVDSPHY for testing 2021-09-28 18:08:03 +02:00
Franck Jullien
a08c5201ad Efinix: improve ifacewriter + misc 2021-09-28 18:06:57 +02:00
Franck Jullien
45961f733b Efinix: instance of dbparser class now in platform 2021-09-28 18:06:23 +02:00
Franck Jullien
b2e09832e5 Efinix: dbparser, add get_gpio_instance_from_pin 2021-09-28 18:04:49 +02:00
Franck Jullien
32f4d246f4 Efinic ConstraintManager improve delete method 2021-09-28 18:04:27 +02:00
Florent Kermarrec
5a35aa9df6 software/libliteeth: Fix missing prototype warnings. 2021-09-28 17:46:23 +02:00
Florent Kermarrec
9a931324c2 get_data_mod: Update pip to pip3 to avoid issues on systems with Python2 still installed. 2021-09-28 16:27:13 +02:00
Karol Gugala
9f1108c2fc libc: refactor picolibc build deps 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:17:30 +02:00
Karol Gugala
b9c4d7ba51 libc: add _impure_ptr definition 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:17:08 +02:00
Karol Gugala
22f50ec7ff libc: add errno include 
This solves missing `__errno` symbol linker errors

Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-28 15:16:34 +02:00
Florent Kermarrec
a588c3b830 software/libc: Disable Atomics support on fgetc/ungetc since seems broken (at least on Rocket). 2021-09-28 14:51:02 +02:00
Florent Kermarrec
061b89beff cpu/picolibc: Add family property to CPUs and directly use it for picolibc. 2021-09-28 14:20:13 +02:00
Florent Kermarrec
b451f102c6 software/libc/stdio: Simplify/Cleanup. 2021-09-28 14:04:24 +02:00
Florent Kermarrec
12c93ea895 litex_sim: Generate gtkw_savefile only with --trace. 2021-09-28 13:32:12 +02:00
Florent Kermarrec
782744bae3 tools/litex_sim/generate_gtkw_savefile: Check main_ram presence. 2021-09-28 10:02:17 +02:00
Florent Kermarrec
de738e153d tools/litex_sim: Avoid double build iteration with pre_run_callback function. 2021-09-28 09:58:43 +02:00
Florent Kermarrec
c98c777bed integration/builder: Avoid picolibc/compiler_rt dependencies when not using the LiteX BIOS & minor cleanups. 2021-09-28 08:57:49 +02:00
Karol Gugala
d101ef7ed0 software: libc: fix Makefile dependecies 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-09-27 23:05:54 +02:00
Florent Kermarrec
01a906add7 software/liblitesdcard: Fix compilation with picolibc. 2021-09-27 18:56:18 +02:00
Florent Kermarrec
727d898a6c software/libliteeth: Update/Fix compilation with picolibc. 2021-09-27 18:54:28 +02:00
enjoy-digital
87f7f3bc45
Merge branch 'master' into dev/litex-sim-gmii-xgmii 2021-09-27 17:47:26 +02:00
Florent Kermarrec
9ab82cacda soc/add_ethernet/etherbone: Fix conflicts/Update. 2021-09-27 17:43:39 +02:00
enjoy-digital
17abdfd12d
Merge pull request #1043 from enjoy-digital/rocket-remove-reset-inserter 
cpu/rocket/core: Remove ResetInserter on adapters.
 2021-09-27 16:34:46 +02:00
Florent Kermarrec
3d32ac3d2e software: Avoid libase renaming to libutils/libcomm and keep readchar/putsnonl retro-compatibility. 
We'll maybe do it but that's probably not the right time. We have to make
the picolibc switch as smooth as possible for users (and so avoid update
as much as possible).

In the long term, it would be good to provide a LiteX C SDK, so we'll make
eventual changes when doing this.
 2021-09-27 16:15:13 +02:00
Florent Kermarrec
ae1d43b965 software/libc/Makefile: Use proper CFLAGS to avoid picolibc warnings and cleanup a bit Makefile. 2021-09-27 16:14:55 +02:00
enjoy-digital
c0b54f0105
Merge pull request #976 from antmicro/libbase-replacement 
Replace libbase with picolibc
 2021-09-27 16:05:24 +02:00