ec080479da
mibuild/sim: use the same architecture we use for others backends
2015-03-27 14:14:49 +01:00
340014dbac
targets: revert use of integers in clocks/timings
2015-03-26 23:45:35 +01:00
9137b91e9e
sdram: remove nbits from modules and databits from GeomSettings
2015-03-26 23:27:37 +01:00
38d24b637e
software/bios/sdram: make seed_to_data static
2015-03-26 23:05:20 +01:00
9a9af17aca
sdram/phy/simphy: remove use of iter
2015-03-26 23:02:23 +01:00
e6de4b1bf9
sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
2015-03-26 22:28:32 +01:00
e79a716425
software/bios/sdram: select the type of data we want to generate for memtest with TEST_RANDOM_DATA (debugging hardware is easier with a simple counter)
2015-03-26 22:16:31 +01:00
257706517e
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
2015-03-26 00:01:42 +01:00
1fc24e66dc
sofware/memtest: use MAIN_RAM_SIZE from mem.h
2015-03-25 19:00:07 +01:00
1a1c9b4420
tools/flterm.py: small clean up
2015-03-25 18:44:08 +01:00
94b62eff8b
libcompiler-rt: add ucmpdi2.o
2015-03-25 17:57:42 +01:00
69e9032d49
sofware/memtest: update bandwidth registers
2015-03-25 17:25:39 +01:00
ff11cb97a9
sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
2015-03-25 17:22:26 +01:00
ba8b24df57
sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
2015-03-25 16:57:38 +01:00
7ea9e2ba89
sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
2015-03-25 16:56:29 +01:00
73c2b7ebaa
tools: add minimal flterm.py (basic flterm.c clone with kernel loading for now)
...
flterm.c is not portable, we need a portable alternative. Once flterm.py will support all flterm features, it will be possible to remove flterm.c.
2015-03-25 16:47:03 +01:00
6492ef1efa
linker-sdram.ld: sdram mem region is now called main_ram
2015-03-25 16:45:19 +01:00
de31103cce
platforms/minispartan6: add ftdi_fifo pins
2015-03-22 11:20:22 +01:00
20207c9c32
liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6)
2015-03-22 11:11:37 +01:00
c77562f44b
liteusb: make oe_n optional on ft2232h phy
2015-03-22 10:56:56 +01:00
ed5746a1fe
liteusb: fix imports
2015-03-22 10:56:29 +01:00
200979fb81
platforms/minispartan6: fix IOStandard/Slew, add FpgaProg programmer, change default clock to 32MHz
2015-03-22 03:37:27 +01:00
a0ee0d8ff6
targets: add minispartan6 (SDRAM working)
2015-03-22 03:29:11 +01:00
92f81409f2
sdram/module: fix tREFI on AS4C16M16
2015-03-22 03:20:02 +01:00
d33729dda9
targets: pipistrello/ppro, fix stupid mistake 10ex --> 1ex...
2015-03-22 02:33:29 +01:00
cf17f06860
targets: fix CLKIN1_PERIOD on ppro and pipistrello
2015-03-22 00:30:21 +01:00
30c2521eb0
sdram: pass sdram_controller_settings to SDRAMSoC
2015-03-21 23:12:18 +01:00
70469e1f37
sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
2015-03-21 21:32:39 +01:00
9bc71f374a
rename sdram mapping to main_ram
2015-03-21 21:01:46 +01:00
c55199deb9
misoclib/soc: add _integrated_ to cpu options to avoid confusion
2015-03-21 20:51:37 +01:00
b75e4b237d
software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone.
...
we now need to add another random addressing test to avoid linear access on L2 cache
2015-03-21 20:29:15 +01:00
7440ccd65b
mibuild/xilinx/programmer: add iMPACT programmer (for sb: I need it in Windows for now since I was not able to get XC3SPROG working)
2015-03-21 20:27:11 +01:00
c60d99583d
sdram/module: add tREFI uniformization to TODO
2015-03-21 18:59:16 +01:00
0f9b0c6f0f
sdram/module: add MT47H128M8 DDR2 (used for a customer)
2015-03-21 18:52:10 +01:00
45eb5090db
sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
2015-03-21 18:41:59 +01:00
a560ba35bd
sdram/module: add AS4C16M16 for minispartan6
2015-03-21 18:38:53 +01:00
1d2e7e8390
mibuild/platforms/minispartan6: adapt to recent changes (able to build simple example)
2015-03-21 18:31:50 +01:00
78b4f313bf
mibuild/platforms/minispartan6: add device parameter (board can be populated with lx9 or lx25)
2015-03-21 18:28:09 +01:00
1a03c340c9
mibuild/platforms: review and fix small mistakes
2015-03-21 18:23:35 +01:00
3a38626556
mibuild/platforms: add minispartan6 (from Matt O'Gorman)
2015-03-21 18:22:26 +01:00
711540e15c
targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics
2015-03-21 18:10:56 +01:00
1c0e306176
targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics
2015-03-21 18:07:10 +01:00
854058a8db
sdram/module: add description and TODO list
2015-03-21 17:44:04 +01:00
52924ee1f2
sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
2015-03-21 17:25:36 +01:00
fd2f8d4bb4
sdram: define MT46V32M16 and use it on m1/mixxeo
2015-03-21 17:04:58 +01:00
de2f1c31d5
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
2015-03-21 16:56:53 +01:00
6e4b7c6cfd
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
...
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
2015-03-21 12:55:39 +01:00
14b1da4018
test_actor: add unittests for SimActor
...
* also implicitly tests for the access of signals during simulation that are
not referenced in any statements
* before, if the busy signal is never used, it is stripped
and could not be accessed in simulation
2015-03-21 10:02:10 +01:00
5f045b7649
sim: keep track of unreferenced items
...
* items that are never referenced in any statements do not end up in the
namespace or in the verilog
* this memorizes items if they can not be found in the namespace and keeps
track of their values
2015-03-21 10:02:10 +01:00
9107710f03
litexxx cores: use default baudrate of 115200 for all tests
2015-03-20 12:22:53 +01:00
Florent Kermarrec
Robert Jordens