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9461 Commits

Author SHA1 Message Date
Navaneeth Bhardwaj a7a746473d Fix missing include in ibex 
Change Ibex to use pythondata-cpu-ibex package and also fix the error of missing include by adding the dependency files first to the list of source files. As mentioned in  lowRISC/ibex#1461.
 2021-10-20 18:26:02 +05:30
Navaneeth Bhardwaj cf2e073b14 Add changes to use Ibex from pythondata-cpu-ibex 2021-10-20 07:28:13 +05:30
Florent Kermarrec 8fa4de5ede cores/video: Interpret CSI Move Up as Clear XY. 2021-10-19 17:24:41 +02:00
Florent Kermarrec 8945d74aa3 litex_setup: Bump pythondata-misc-opentitan (and update Get SHA1 command). 2021-10-19 15:47:24 +02:00
Florent Kermarrec b9545c2276 cpu/ibex: Add local patch to fix missing import. 2021-10-19 15:43:27 +02:00
enjoy-digital f4bd729d28
Merge pull request #1070 from navan93/ibex-irq-support 
Fix the support for Ibex.
 2021-10-19 15:43:12 +02:00
Florent Kermarrec 78237fffd9 cores/cpu: Avoid complex port types on microwatt_wrapper. 
microwatt_wrapper.vhdl was introduced for this since some toolchains don't
support complex VHDL ports types on verilog instances (ex previous version
of Vivado).
 2021-10-19 15:04:12 +02:00
Florent Kermarrec d1bb62b5fb litex_setup: Bump pythondata-cpu-microwatt to 0xdad611c. 2021-10-19 14:44:12 +02:00
enjoy-digital 2a97b6a1c1
Merge pull request #1067 from antmicro/fix-microwatt-synthesis 
Fix microwatt synthesis
 2021-10-19 14:43:11 +02:00
Florent Kermarrec 4335e305f7 cpu/mor1kx: Add or1k-linux to gcc_triple. 2021-10-19 14:42:15 +02:00
Florent Kermarrec 4494e98549 litex_setup: Add link to bootlin prebuilt PowerPC/OpenRisc toolchains. 2021-10-19 14:41:42 +02:00
enjoy-digital adf5665f21
Merge pull request #1072 from AndrewD/master 
efinix and general improvements
 2021-10-19 13:46:09 +02:00
Andrew Dennison a043b2536d efinix: abort if scripts fail 
* get obscure downstream errors when the scripts blindly continue
 2021-10-19 12:51:32 +11:00
Andrew Dennison f426872e0c efinix: read pll names from database 2021-10-19 12:51:32 +11:00
Andrew Dennison 1fd99b366a soc: report System clock to 3dp 2021-10-19 12:51:32 +11:00
Andrew Dennison 0e164bb23c build/generic_platform: include identifier in ValueError 
* show which identifier is incorrectly specified
 2021-10-19 12:49:05 +11:00
Navaneeth 0fbaa51c71 Change to common isr handler 2021-10-19 07:14:36 +05:30
Andrew Dennison 053e540b8a soc/csr: ValueError if write would be truncated in simulation 2021-10-19 10:42:52 +11:00
Andrew Dennison 04e9ffa2b2 soc/csr: Document simulation side effects of read/write 2021-10-19 10:42:52 +11:00
Florent Kermarrec 467c1b9b88 builder: Move Meson check to _check_meson and only do it when using BIOS. 2021-10-18 18:48:47 +02:00
Navaneeth ef8bab4c11 Add support for Ibex interrupt 
Initial support for a working Ibex interrupt. Tested in Verilator.
 2021-10-18 20:02:05 +05:30
Florent Kermarrec 2a109c3a3e integration/builder: Add Meson install/version check. 2021-10-18 08:41:51 +02:00
Florent Kermarrec f92a185109 litex_setup: Fix git checkout to specific version (we are using short sha1 hashes). 2021-10-18 08:19:11 +02:00
navaneeth c8a83461b4 Add initial changes to add IRQ support 
In the waveform IRQ pending seems to be going high but the call to ISR() doesn't happen.
 2021-10-17 12:32:31 +05:30
navaneeth b2b0ba66e5 Fix the support for Ibex. 
Take care of the module change in instantiation of Ibex core.
 2021-10-16 16:29:00 +05:30
enjoy-digital 57002cf3fc
Merge pull request #1069 from trabucayre/efinix_timing_model 
efinix: don't hardcode timing model
 2021-10-16 08:48:19 +02:00
Gwenhael Goavec-Merou 627363906c efinix: don't hardcode timing model 2021-10-16 07:20:17 +02:00
Florent Kermarrec 306bdcaed8 fhdl/verilog: Fix regression introduced in to_signed function. 2021-10-15 21:46:42 +02:00
enjoy-digital 942d3165bd
Merge pull request #1068 from mmicko/efinix_pgm_fix 
efinix: set defaults for efx_pgm pass
 2021-10-15 17:42:12 +02:00
Miodrag Milanovic 8692ddfbff Set defaults for efx_pgm pass 2021-10-15 16:40:01 +02:00
Florent Kermarrec 37dd6c1edb fhdl/verilog: Update header. 2021-10-15 15:25:23 +02:00
Florent Kermarrec 3b78fd928d fhdl/verilog: Remove blocking_assign (not used with LiteX). 2021-10-15 15:20:01 +02:00
Florent Kermarrec fe2998a19c fhdl/verilog: Remove create_clock_domains (not used in LiteX). 2021-10-15 15:12:30 +02:00
Florent Kermarrec 8c3508e7f5 fhdl/verilog: Remove dummy_signal (no longer used). 2021-10-15 15:09:41 +02:00
Florent Kermarrec f692f50d06 fhdl/verilog: Remove reg_initialization (always enabled in LiteX). 2021-10-15 15:01:41 +02:00
Florent Kermarrec 84e8fd0f9e fhdl/verilog: Add larger separators. 2021-10-15 14:55:46 +02:00
Florent Kermarrec 5a2399b037 fhdl/verilog: Remove display_run (not used in LiteX). 2021-10-15 14:43:42 +02:00
Florent Kermarrec 8aad25ae2b fhdl/verilog: Create _print_cat/_print_replicate, start cleaning up convert. 2021-10-15 14:25:33 +02:00
Florent Kermarrec 2c98ad94b5 fhdl/verilog: Create _print_operator/_print_slice, move code outside _print_expression and cleanup/simplify. 2021-10-15 13:54:06 +02:00
Florent Kermarrec cdfb8d141a fhdl/verilog: Simplify _print_signal/_print_constant, add comments to _print_expression. 2021-10-15 11:51:39 +02:00
Florent Kermarrec a18107f795 fhdl/verilog: Give more explict names to print functions. 2021-10-15 11:27:34 +02:00
Florent Kermarrec 86178ed2d9 fhdl/verilog: Update Reserved Keywords (from IEEE 1800-2017) and minor cleanup. 2021-10-15 11:06:31 +02:00
Michal Sieron 5b166b3aa4 Fix microwatt synthesis 
Microwatt uses now 29 bit wishbone addresses, so 3 additional bits for
compatibility are no longer needed.

Rest is minimal set of changes that was needed to make it build.
 2021-10-14 19:57:11 +02:00
Florent Kermarrec adf30928d4 build/efinix/efinity: Simplify get_pin_direction with direction/name already set to signals when generating the verilog. 2021-10-14 19:12:00 +02:00
Florent Kermarrec 2628140e8a soc_core: Also add "no_we" support to integrated_main_ram (and improve add_ram/add_rom calls). 2021-10-14 10:18:17 +02:00
Florent Kermarrec 8316fbf14b build/efinix/common: Fix EfinixAsyncResetSynchronizerImpl. 
SR_VALUE is set to 0 by default and needs to be set to 1.
 2021-10-13 16:31:47 +02:00
Florent Kermarrec f0a3fcfefa build/efinix: Improve error message when Efinity toolchain is not found. 2021-10-13 14:41:44 +02:00
Florent Kermarrec fd354c5759 gen/fhdl/memory: Fix dual clock memory pattern (previous pattern is no longer supported by Yosys), thanks @gregdavill. 
See https://github.com/enjoy-digital/litex/issues/1003.
 2021-10-13 11:33:43 +02:00
Florent Kermarrec 8fbd1b84a4 gen/fhdl: Use a local emit_verilog function for Memory. 
With the various FPGA now supported, being able to generate valid verilog patterns
that will be infered correctly is now complicated.

Use our local version of emit_verilog to be able to specialize more easily the generated
code.

This will also allow use to progressively remplace Migen's Memory.
 2021-10-13 10:58:49 +02:00
Florent Kermarrec 269b84eca4 build/efinix: Move tweaked Memory to build/efinix for now. 2021-10-13 09:51:47 +02:00