4c978bf463
build/generic_toolchain: Add add_false_path_constraint and remove it from altera/quartus, lattice/trellis.
2022-06-24 10:24:01 +02:00
6b59eb5cfe
build/generic_toolchain/add_period_constraint: Integrated rounding to lowest picosecond and remove add_period_constraint from altera/quartus.
2022-06-24 10:19:59 +02:00
08a3b0ae4a
build/generic_toolchain: Add build_placement_constraints method and switch other methods to *args, **kwargs for now.
2022-06-24 10:17:02 +02:00
1ecb9cec0a
build/generic_toolchain: Rename constraints methods to build_io_constraints/build_timing_constraints.
2022-06-24 10:12:36 +02:00
08cc384a0c
build/generic_toolchain: Fix build/copyrights and do minor cosmetic changes.
2022-06-24 09:51:46 +02:00
9db1d9e49f
toolchain: implement generic toolchain and devices toolchain refactoring
2022-06-24 09:20:42 +02:00
ee1af96ab7
CHANGES: Update.
2022-06-22 18:13:49 +02:00
1a90549fa3
interconnect/axi/axi_full: Switch to our own AXI Interconnect (Shared & Crossbar).
...
We were not able to simulate verilog_axi interconnect/crossbar correctly since to what
seems to be a simulation mismatch. The code also seems to requires fixing some synthesis
issues with Yosys. When tested with Vivado, the SoC was also miss-behaving (not booting
correctly).
The simulation mismatch issue is logged here: https://github.com/enjoy-digital/litex_verilog_axi_test/issues/1
Since we already had our own AXI-Lite interconnect, creating our AXI interconnect can be
largely based on it with only minor modifications, so switch to it. This also allow simplification
in the interconnect selection/instance.
2022-06-20 19:51:31 +02:00
573479b395
interconnect:axi/axi_lite/interconnect: Cosmetic cleanups.
2022-06-20 19:13:44 +02:00
bb1702e6d5
integration/export: Align MEM_REGIONS for BIOS display with mem_list.
...
Before:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x01000000 0x2000
AXI_RAM 0x00010000 0x1000
AXI_DP_RAM_A 0x00011000 0x1000
AXI_DP_RAM_B 0x00012000 0x1000
AXI_RAM_REG 0x00013000 0x1000
AXI_RAM_FIFO 0x00014000 0x1000
AXI_RAM_XBAR 0x00100000 0x10000
AXI_RAM_INT 0x00200000 0x10000
CSR 0x82000000 0x10000
After:
litex> mem_list
Available memory regions:
ROM 0x00000000 0x10000
SRAM 0x10000000 0x2000
AXI_RAM 0x00010000 0x1000
AXI_DP_RAM_A 0x00011000 0x1000
AXI_DP_RAM_B 0x00012000 0x1000
AXI_RAM_REG 0x00013000 0x1000
AXI_RAM_FIFO 0x00014000 0x1000
AXI_RAM_XBAR 0x00100000 0x10000
AXI_RAM_INT 0x00200000 0x10000
CSR 0xf0000000 0x10000
2022-06-20 15:21:16 +02:00
b00d22f56a
Merge pull request #1334 from antmicro/move_to_f4pga
...
Move from deprecated Symbiflow to F4PGA
2022-06-20 11:56:42 +02:00
b8ee713dba
Merge pull request #1331 from cr1901/gowin-win
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Gowin: Fix `copyfile` paths
2022-06-20 11:32:47 +02:00
b66bd171cc
litex_setup: Use recursive clone for litex_verilog_axi.
2022-06-20 11:23:00 +02:00
32d1589fb8
litex_setup: Move valentyusb to Misc Cores and also install litex_verilog_axi.
2022-06-20 11:01:47 +02:00
9b6c9e6630
litex_setup: Switch to specific branch when initializing repositories.
2022-06-20 10:43:30 +02:00
ef2f1bd65b
Merge pull request #1333 from gsomlo/gls-noboot-warning
...
bios/main: Wrap CONFIG_NO_BOOT around boot_sequence()
2022-06-20 08:37:03 +02:00
b86629a615
Merge pull request #1335 from benstobbs/valentyusb-proper-install
...
Move valentyusb install to litex_setup.py
2022-06-20 08:36:44 +02:00
ca97d91424
clone correct valentyusb branch
2022-06-19 12:58:01 +01:00
db3fa1efc7
move valentyusb install to litex_setup.py
2022-06-19 12:51:14 +01:00
cbd873a33e
test: FifoSyncMacro: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
839ca545a4
build: quicklogic: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
2c0f59536c
build: xilinx: Use F4PGA instead of deprecated Symbiflow
2022-06-17 16:27:25 +02:00
0941459061
integration/soc: Add initial AXI-full support.
...
Main bus can now be switched to AXI-full with --bus-standard=axi.
The interconnect will be AXI-Full (Using Alex Forenchich's verilog_axi
Interconnect and Crossbar) but ROM/SRAM will still be in AXI-Lite (Will
be switched to AXI-full in the future).
This gives a first working version that can be used for further improvements.
Note that the interconnect can also be selected by --bus-interconnect=shared or
crossbar.
2022-06-17 16:21:31 +02:00
8394e93742
interconnect/axi/axi_full: Add AXI Interconnect (Shared and Crossbar).
...
For now reusing Alex Forenchich's modules wrapped with LiteX.
2022-06-17 16:07:05 +02:00
bc667c6456
interconnect/axi/axi_full/AXIInterface: Add name/bursting parameters.
...
To add compatibility with AXILiteInterface and allow dynamic selection.
2022-06-17 16:04:25 +02:00
333aadbf6e
integration/soc/SoC: Switch to finalize and finalize submodule only at the end.
...
This avoid elaborating submodules before adding the final modules and gives more
flexibility.
2022-06-17 16:01:28 +02:00
4c0a943996
interconnect/axi: Create axi directory and split code by type/functionnality.
...
AXI code is now too large to be contained in a single file, splitting code by type/functionnality
will simplify future additions.
2022-06-16 18:53:12 +02:00
c4e07e2a5b
integration/soc: Allow Bus Interconnect to use either InterconnectShared or Crossbar and add --bus-interconnect command line parameter.
2022-06-16 17:47:13 +02:00
6942e3240c
interconnect/axi/AXIDownConverter: Switch to AXI-Full (Inspired from AXIUpConverter).
2022-06-16 16:16:49 +02:00
f9f3557bca
bios/main: Wrap CONFIG_NO_BOOT around boot_sequence()
...
This eliminates a "defined but unused" warning on the
`boot_sequence()` function when `main.c` is compiled
with `#define CONFIG_NO_BOOT`.
2022-06-16 08:22:14 -04:00
50553a45ec
integration/soc/add_adapter: Create data_width_convert/bus_standard_convert functions and improve code genericity.
...
This already cleanup/simplify code and will also allow eventual order changes in the conversions.
2022-06-16 11:53:47 +02:00
3e10576fcd
build/gowin: Fix bitstream copy to gateware directory.
2022-06-15 21:45:19 -04:00
b6f4302e8e
integration/soc/add_adapter: Add AXI2AXILite and AXI2Wishbone support.
2022-06-15 19:37:04 +02:00
da5d9ecf9b
interconnect/axi: Add AXIDownConverter (through AXI-Lite) and AXIConverter.
2022-06-15 19:34:47 +02:00
ac800da43c
cpus: Make use of new automatic AXI <-> AXI-Lite/Wishbone conversion.
2022-06-15 18:15:59 +02:00
d7e599c04f
integration/soc/add_adapter: Add AXI<->Wishbone and AXI<->AXI-Lite support.
...
Allow directly passing AXI interfaces to add_slave/add_master and thus simplify user code.
2022-06-15 17:58:39 +02:00
f62ba0f66d
integration/soc: Simplify add_config and use it for all config parameters.
2022-06-15 17:34:07 +02:00
1d7aa9c438
cpu/openc906: Switch to AXI-Lite instead of Wishbone and minor cleanup.
2022-06-15 16:51:50 +02:00
eebb639c12
Merge pull request #1328 from Icenowy/c906
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[WIP] soc/cores/cpu: add initial OpenC906 support
2022-06-15 11:23:14 +02:00
8fa9178716
Merge pull request #1326 from Technosystem-Labs/openocd_0_11
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Updated OpenOCD stream for expr use
2022-06-15 11:10:02 +02:00
a4de315772
Merge pull request #1329 from Icenowy/altpll-fix
...
Misc fixes to Altera PLL support
2022-06-15 10:52:24 +02:00
d1a456a545
integration/export/_get_csr_addr: Add back parenthesis around CSR_BASE + X.
2022-06-14 15:03:18 +02:00
8ffabe3bcb
soc/cores/cpu: add initial OpenC906 support
...
It's only boot tested in sim and build tested in Vivado now, and it
requires a FPGA > 100k LUT4 (XC7A100T currently does not fit).
The ISR code is based on Rocket one.
These Python code depends on a forked version of OpenC906 at [1].
[1] https://github.com/Icenowy/openc906/tree/fpga-optimization
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-14 02:04:58 +08:00
6d11d1991b
build/altera: Add derive_pll_clocks to SDC file
...
Quartus software wants a derive_pll_clock sentence in SDC file to enable
automatic PLL clock derivation, and by test this sentence is harmless
even when no PLL exists.
Add this sentence to to the generated SDC file.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 22:51:54 +08:00
58f9a79cf3
cores/clock/intel_common: fix N factor not get passed to ALTPLL primitive
...
The N factor is currently ignored when creating ALTPLL instance.
As Quartus will internally decide N based on all dividers, just multiply
N to all clock outputs' individual divider.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me>
2022-06-13 22:51:20 +08:00
49d0463394
integration/export/csr: Allow disabling CSR_BASE #define/reuse when not wanted.
...
Reuse of external defined CSR_BASE has been added for some use-cases, allowing more
flexilibity but also complicating direct read of base addresses for users in csr.h.
with_csr_base_define parameter has been added, allowing disabling CSR_BASE #define/reuse
when set to False.
2022-06-09 16:39:29 +02:00
8ccfc96b1a
build/osfpga: Fix device support.
2022-06-08 18:25:50 +02:00
59ca268de9
Updated OpenOCD stream for expr use deprecation in v0.11
2022-06-08 15:07:58 +02:00
eeed11edea
build/osfpga: Remove .init workaround since fixed in toolchain.
2022-06-07 12:34:42 +02:00
24e483026d
Merge pull request #1325 from AEW2015/litex_dev
...
adding JTAG support for the xcau, Xilinx Artix UltraScale+
2022-06-07 12:11:57 +02:00
Florent Kermarrec
Gwenhael Goavec-Merou
Ben Stobbs
Robert Szczepanski
Gabriel Somlo
William D. Jones
Icenowy Zheng
Mikołaj Sowiński