Commit Graph

7077 Commits

Author SHA1 Message Date
Michal Sieron 514754bedf Get pythondata-software-picolibc from antmicro 2021-09-16 10:41:05 +02:00
Michal Sieron fc0fa88e33 Update litex_setup.py to use forked codebase 2021-09-16 10:41:05 +02:00
Michal Sieron 6de59bdbc0 Incorporate picolibc into the build process
Right now it is still limited as it compiles only for one target,
but it should be possible to build BIOS with one command

Tested with digilent_arty.py
2021-09-16 10:41:05 +02:00
Michał Sieroń e25ca4082b Apply patch removing need for most of libbase 2021-09-16 10:41:05 +02:00
Florent Kermarrec 05b960d09b CHANGES: Update. 2021-09-15 12:08:30 +02:00
enjoy-digital 02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll
Fix premature selection of full PLL config with no feedback
2021-09-15 08:52:59 +02:00
George Hilliard 91ec6e0da8 clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond
Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs.  Emit the same attributes that Diamond's PLL tool does.
2021-09-15 00:07:43 -05:00
George Hilliard 6733a3e3e6 clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search 2021-09-15 00:07:43 -05:00
Florent Kermarrec 88d302d4db soc/alloc_region: Ensure allocated Region is aligned on size. 2021-09-14 18:08:07 +02:00
Florent Kermarrec 694878a35a integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints.
Some boards require specific constraints, so disable them in this case and put constraints in the target file.
2021-09-13 19:32:50 +02:00
Florent Kermarrec cb7b0f44cf tools/litex_sim: Fix mem_map. 2021-09-13 11:33:16 +02:00
Florent Kermarrec e0e9311ceb interconnect/wishbone: Specify Wishbone version (#999). 2021-09-08 17:33:01 +02:00
Florent Kermarrec 6c2bc02323 build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names.
This makes it similar to add_platform_command and add more flexibility to constraint the design.
2021-09-08 16:14:58 +02:00
Florent Kermarrec 0222697f21 liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size.
On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.

This will be less accurate but will still provide representative results which
is the aim of this test.
2021-09-08 09:10:21 +02:00
Florent Kermarrec 10c4523c32 soc/add_spi_flash: Add rate parameter to select 1:1 SDR or 1:2 DDR PHY. 2021-09-07 15:09:05 +02:00
Florent Kermarrec 575af6fc60 litespi/integration: Review/Cleanup #1024.
Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
2021-09-07 14:36:13 +02:00
enjoy-digital aff2aefa72
Merge pull request #1024 from antmicro/litespi_refactor
litex: adding litespi to simulation, making litespi compatible with new implementation
2021-09-07 13:17:40 +02:00
enjoy-digital bdd4717daa
Merge pull request #1028 from wuhanstudio/fix-syntax-error
fix: missing colon syntax error
2021-09-07 13:00:48 +02:00
wuhanstudio 5d9880888c fix: missing colon syntax error 2021-09-07 11:21:41 +01:00
Florent Kermarrec a6f9ac58bb build/sim/common: Review/Cleanup #1021 for consistency with other backends. 2021-09-07 09:44:43 +02:00
enjoy-digital 2b700057b7
Merge pull request #1021 from antmicro/ddr_sim
litex: Enable simulation of DDR IO by adding oddr/iddr/ddrtristate simulation models.
2021-09-07 09:38:14 +02:00
Florent Kermarrec 7c50f52a57 tools/litex_sim: Improve RAM/SDRAM integration and make closer to LiteX-Boards targets.
litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
2021-09-07 09:27:51 +02:00
enjoy-digital 1598b5958d
Merge pull request #1017 from asadaleem-rs/master
customize main ram size from command line argument
2021-09-07 09:15:55 +02:00
Florent Kermarrec e257d91d46 cpu/vexriscv: Review/Cleanup #1022.
Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
2021-09-07 09:04:47 +02:00
enjoy-digital 6b792dce54
Merge pull request #1022 from tcal-x/vex-dcache
Restructure config flags for dcache/icache presence in Vex.
2021-09-07 08:46:03 +02:00
Tim Ansell bafe32dd13
Merge pull request #1020 from shenki/binutils-fixes
Binutils fixes
2021-09-06 17:16:56 -07:00
Pawel Sagan ad0fcc22e6 litex: adding legacy mode for litespi
Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
2021-09-03 09:42:41 +02:00
Florent Kermarrec fa5fd765a4 interconnect/packet: Add dummy to omit list, fixes #1018. 2021-09-02 18:02:16 +02:00
Florent Kermarrec 7bd06d178f cores/clock/xilinx_s6: Remove power_down (no i_PWRDWN input on PLL_ADV). 2021-09-02 15:12:16 +02:00
Pawel Sagan 3cf6126663 litex: adding explicit clk signal to ODDR/IDDR models in DDRTristate 2021-09-02 14:33:16 +02:00
Piotr Binkowski 25e0153dd5 litex_sim: use flash model in simulation 2021-09-02 14:33:16 +02:00
Pawel Sagan 837de615e6 liblitespi: adjusting code to oddr/iddr litespi implementation
Changing litespi registers configuration to be compatible
with a new implementation.
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
2021-09-02 14:33:11 +02:00
Pawel Sagan 0c91bb7b96 litex_sim: adding spi-flash option to simulation
Signed-off-by: Paweł Sagan <psagan@antmicro.com>
2021-09-02 14:22:34 +02:00
Florent Kermarrec 8c50366d15 litespi/spiflash: Use shorted message when first SPI Flash block is erased and freq test cannot be done. 2021-09-02 11:26:56 +02:00
Florent Kermarrec 103b108ea8 soc/add_spi_flash: Pass device to LiteSPIPHY for proper clk primitive instantiation. 2021-09-02 11:26:15 +02:00
Tim Callahan ca563dd5f3 Restructure config flags for dcache/icache presence in Vex.
Signed-off-by: Tim Callahan <tcal@google.com>
2021-09-01 11:24:44 -07:00
enjoy-digital 315fbe18cb
Merge pull request #1016 from antmicro/jboc/lpddr5
soc/software/liblitedram: fix max error count computation
2021-09-01 11:16:07 +02:00
enjoy-digital 931a2b34ce
Merge pull request #1019 from G33KatWork/fix_setup
Add docs static files to package_data in setup.py
2021-09-01 11:14:47 +02:00
Florent Kermarrec feeb2bfe31 tools/litex_contributors: Add special cases for companies to replace individuals with company name/email.
Avoid doing it manually.
2021-09-01 11:09:26 +02:00
Joel Stanley 722772a3d8 microwatt: Fix relocation error when linking
When building with GCC 11:

../libbase/crt0.o: in function `_start':
litex/soc/cores/cpu/microwatt/crt0.S:54:(.text+0x38): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fdata' defined in .data section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:55:(.text+0x3c): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_edata' defined in .data section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:56:(.text+0x40): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fdata_rom' defined in *ABS* section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:68:(.text+0x68): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fbss' defined in .bss section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:69:(.text+0x6c): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_ebss' defined in .bss section in bios.elf
litex/soc/cores/cpu/microwatt/crt0.S:80:(.text+0x90): relocation truncated to fit: R_PPC64_GOT16_DS against symbol `_fstack' defined in .bss section in bios.elf
boot.o: in function `copy_file_from_sdcard_to_ram':
litex/soc/software/bios/boot.c:622:(.text+0x18): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'
litex/soc/software/bios/boot.c:627:(.text+0x5c): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+8
litex/soc/software/bios/boot.c:633:(.text+0x8c): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+10
litex/soc/software/bios/boot.c:639:(.text+0xdc): relocation truncated to fit: R_PPC64_TOC16_DS against `.toc'+18
litex/soc/software/bios/boot.c:650:(.text+0x128): additional relocation overflows omitted from the output

This is because we pass -mcmodel=small. As the PowerPC ELF ABI
describes, the small code model restricts the relocations to 16-bit
offsets[1]. If we omit the option we get the default, which is the
medium model allowing 32-bit offsets.

http://openpowerfoundation.org/wp-content/uploads/resources/leabi/content/dbdoclet.50655240_19143.html

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-01 18:02:19 +09:30
Pawel Sagan 8aa7c1b9dd litex: adding oddr/iddr/ddrtristate simulation models
Signed-off-by: Pawel Sagan <psagan@antmicro.com>
2021-09-01 10:25:21 +02:00
Joel Stanley d91c8dcfa2 bios: Fix build-id link error
New version of binutils contain stricter checks for sections that are
not included in the linker script, resulting in this error:

 ld: error: no memory region specified for loadable section `.note.gnu.build-id'

Disable this feature as there is no use for it on bare metal systems.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-01 15:41:24 +09:30
Joel Stanley c74e3642b3 bios: Fix PHDR link error
binutils 2.34 contains stricter checks for sections that are not
included in the linker script, resulting in this error:

 ld: bios.elf: error: PHDR segment not covered by LOAD segment

From the 2.34 NEWS:

  The ld check for "PHDR segment not covered by LOAD segment" is more
  effective, catching cases that were wrongly allowed by previous versions of
  ld.  If you see this error it is likely you are linking with a bad linker
  script or the binary you are building is not intended to be loaded by a
  dynamic loader.  In the latter case --no-dynamic-linker is appropriate.

As the BIOS runs bare metal, we do not need to emit a PHDR segment.

Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-09-01 15:33:44 +09:30
Andreas Galauner b0470c7da1 Add docs static files to package_data in setup.py
This patch adds the static files needed for the documentation to the
`package_data` field in `setup.py`.

I ran into failures when generating documentation after installing litex
using pipenv which didn't copy these files which in turn caused the
documentation generation to fail.

This change causes all files in the `static` subfolder of the
litex.soc.doc module to be installed as well.
2021-09-01 05:23:51 +02:00
asadaleem-rs 8428e89f09 customize main ram size from command line argument 2021-08-30 17:36:40 +05:00
Jędrzej Boczar f943092bb5 soc/software/liblitedram: fix max error count computation
READ_CHECK_TEST_PATTERN_MAX_ERRORS was being computed incorrectly
which could result in integer underflows when computing core via
(max_errors - errors). This could happen e.g. when using
DFIRateConverter, which modifies DFII_PIX_DATA_BYTES. Now we use
DFII_PIX_DATA_BYTES in the equation so this should not happen.
2021-08-30 12:54:49 +02:00
enjoy-digital 1d27e25cbb
Merge pull request #1015 from antmicro/ddr-tristate
build: add DDRTristate
2021-08-27 19:12:45 +02:00
Piotr Binkowski 84896f73ac build: add DDRTristate 2021-08-27 13:51:58 +02:00
enjoy-digital 53750715d7
Merge pull request #1013 from antmicro/reset-tx-uart-pad
Set TX UART pin high on reset
2021-08-26 18:54:18 +02:00
Michal Sieron 47291e07f7 Set TX UART pin high on reset
Without this we get corrupted data on the output after
SoC reset. It was present there, but got removed in
908e72e65b refactor.
Fixes #991
2021-08-26 18:07:03 +02:00