Franck Jullien
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be8e825a0b
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efinix: fix EfinixTristateImpl
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2022-02-01 21:14:35 +01:00 |
Florent Kermarrec
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78ecf50ad5
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cores/jtag: Make primitive selection more flexible (and simplify new devices support).
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2022-02-01 12:44:18 +01:00 |
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Florent Kermarrec
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b59fdae588
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cores/jtag: Simplify/Cleanup.
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2022-02-01 11:32:04 +01:00 |
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Florent Kermarrec
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1c5d91dce1
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cores/jtag: Deprecate JTAG Atlantic support (Advantageously replaced by JTAG-UART).
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2022-02-01 11:19:36 +01:00 |
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Florent Kermarrec
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6f6a10db5c
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CHANGES: Update.
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2022-01-31 17:00:51 +01:00 |
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enjoy-digital
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0711998dab
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Merge pull request #1191 from david-sawatzke/dev/doc_atomic_writes
Fix generation of documentation of `atomic_write` CSRStorage
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2022-01-31 16:48:02 +01:00 |
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Florent Kermarrec
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52a0497032
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altera/jtag: Minor cosmetic cleanups, avoid some duplications.
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2022-01-31 16:08:08 +01:00 |
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Florent Kermarrec
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b2448ba50e
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soc/cores/jtag: Review/Cleanup JTAGTAPFSM and avoid specific CorrectedOngoingResetFSM.
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2022-01-31 16:07:50 +01:00 |
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enjoy-digital
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40799332a0
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Merge pull request #1188 from jevinskie/jev/altera-jtag
Add JTAGbone support for Altera Max 10 and Cyclone 10 LP
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2022-01-31 16:07:30 +01:00 |
David Sawatzke
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a981f935f2
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Fix generation of documentation of `atomic_write` CSRStorage
Can't decrement a range by 1, this (probably) never worked.
Also improves the generated text.
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2022-01-30 18:05:52 +01:00 |
Jevin Sweval
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349087a8c0
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Add JTAGbone support for Altera Max 10 and Cyclone 10 LP
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2022-01-29 13:27:53 -08:00 |
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Florent Kermarrec
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bfad61cd2a
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build/builder: Simplify/Review #1190.
- Only do copy in Builder.
- Use relative path for copied files (will be useful to create self-contained gateware archive).
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2022-01-28 19:32:12 +01:00 |
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enjoy-digital
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3dcc6180f3
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Merge pull request #1190 from fjullien/copy_files
Copy files
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2022-01-28 19:11:40 +01:00 |
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Florent Kermarrec
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4de54387d3
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soc: Replace remaining add_wb_master call by self.bus.add_master.
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2022-01-28 18:41:52 +01:00 |
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Florent Kermarrec
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162231fb8f
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cores/prbs: Define PRBS_CONFIG constants and use them in code. Also simplify PRBSGenerator data selection.
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2022-01-28 11:29:47 +01:00 |
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Franck Jullien
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598d678f59
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Add an argument to add_source for files copy
With this argument, added files will be copied to the gateware
directory and referenced in the project from this new location.
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2022-01-28 09:53:06 +01:00 |
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Franck Jullien
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5fd7c758a1
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efinity: don't add unknown language files to sources
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2022-01-27 23:14:46 +01:00 |
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enjoy-digital
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ccd3ab17be
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Merge pull request #1187 from fjullien/efinix_fix
efinix: fix pull up/down constraint
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2022-01-27 20:08:12 +01:00 |
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enjoy-digital
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4696e39560
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Merge pull request #1186 from trabucayre/xilinx_symbiflow_zynq
litex/build/xilinx/symbiflow: adding zynq (010 & 020) support
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2022-01-27 20:07:36 +01:00 |
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Franck Jullien
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b134fcc9c0
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efinix: fix pull up/down constraint
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2022-01-27 17:11:38 +01:00 |
Gwenhael Goavec-Merou
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21ff32f800
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litex/build/xilinx/symbiflow: adding zynq (010 & 020) support
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2022-01-27 09:03:22 +01:00 |
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Florent Kermarrec
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e8be391504
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setup.py: Deprecate lxterm/lxserver/lxsim short names.
These were no longer really used and was confusing.
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2022-01-26 15:14:54 +01:00 |
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Florent Kermarrec
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6b4d5cd3e1
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README: Add --config to install command.
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2022-01-26 14:51:54 +01:00 |
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Florent Kermarrec
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af26d939d0
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litex_setup: Declare python3 in top and use it.
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2022-01-26 14:49:02 +01:00 |
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enjoy-digital
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f82f769794
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Merge pull request #1185 from benstobbs/master
litex_setup.py on Windows: Change install "python3" to current interpreter
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2022-01-26 14:45:00 +01:00 |
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Florent Kermarrec
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4ab45d72a8
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litex_setup: Add --status argument to display Git status of repositories.
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2022-01-26 14:44:04 +01:00 |
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Florent Kermarrec
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d2d8d902e1
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litex_setup/print_status: Add underline parameter and use it.
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2022-01-26 14:20:41 +01:00 |
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Florent Kermarrec
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419d605e38
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build/toolchains: Specify passed toolchain when unknown.
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2022-01-26 11:56:22 +01:00 |
Ben Stobbs
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e0149eb814
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change repo install python interpreter to current interpreter
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2022-01-25 22:46:33 +00:00 |
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enjoy-digital
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3020344fd8
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Merge pull request #1184 from trabucayre/yosys_nextpnr_zynq
litex/build/xilinx/yosys_nextpnr: adding zynq7 and xc7z010 & xc7z020 support
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2022-01-25 22:27:01 +01:00 |
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enjoy-digital
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7acdac2e51
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Merge pull request #1183 from trabucayre/fix_yosys_synth
litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE
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2022-01-25 22:26:18 +01:00 |
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Gwenhael Goavec-Merou
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f00fe1b1d8
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litex/build/xilinx/yosys_nextpnr: adding zynq7 and xc7z010 & xc7z020 support
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2022-01-25 21:58:03 +01:00 |
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Gwenhael Goavec-Merou
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f8acc5f506
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litex/soc/cores/clock/xilinx_common: fix yosys synth: replace FD by FDCE
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2022-01-25 21:44:02 +01:00 |
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Florent Kermarrec
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77c6cdd78e
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cores/clocks/lattice_ecp5: Rename ECP5Delay to ECP5DynamicDelay and adapt style for consistency.
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2022-01-25 11:09:15 +01:00 |
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Florent Kermarrec
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ea6bb3dd80
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test/test_clock: Add minimal ECP5Delay test (syntax), rename tests with underscore.
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2022-01-25 10:49:33 +01:00 |
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enjoy-digital
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6ff8b6e4ed
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Merge pull request #1173 from sergachev/ecp5_delay
clock/lattice_ecp5: add ECP5 dynamic delay DELAYF primitive support
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2022-01-25 10:44:53 +01:00 |
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enjoy-digital
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d059111c92
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Merge pull request #1180 from suarezvictor/master
Add yosys+nextpnr toolchain support
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2022-01-24 19:02:02 +01:00 |
Victor Suarez Rovere
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6d7f8888ac
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Add yosys+nextpnr toolchain support
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2022-01-24 13:35:12 -03:00 |
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enjoy-digital
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6b3eda16f2
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Merge pull request #1179 from Technosystem-Labs/vexriscv_hw_breakpoints
Added Vexriscv hardware breakpoint variants for Mini and Lite.
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2022-01-24 08:16:39 +01:00 |
Mikolaj Sowinski
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9e0d8b3f41
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Added Vexriscv hardware breakpoint variants for Mini and Lite.
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2022-01-24 00:00:26 +01:00 |
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enjoy-digital
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8d3f12ebbd
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Merge pull request #1178 from sergachev/gowin_emcu
Enable LiteX BIOS on Gowin EMCU ARM core
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2022-01-23 21:01:06 +01:00 |
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enjoy-digital
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57fef500a7
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Merge pull request #1177 from yetifrisstlama/i2c
bitbang.py: initialize SCL / SDA lines to high on reset
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2022-01-23 21:00:20 +01:00 |
Ilia Sergachev
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f36619987b
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software/bios: update comment
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2022-01-23 16:57:33 +01:00 |
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Ilia Sergachev
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85f892227a
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cores/cpu/gowin: re-enable write access to csr bus
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2022-01-23 16:34:47 +01:00 |
Michael Betz
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e4ceaa7cc2
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bitbang.py: initialize SCL / SDA lines to high on reset
* otherwise might block the I2C bus on reset
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2022-01-23 16:11:34 +01:00 |
|
Ilia Sergachev
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0f44723957
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cores/cpu/gowin: fix isr table optimization and uart init
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2022-01-23 15:37:00 +01:00 |
|
Ilia Sergachev
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d4c12a5231
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cores/cpu/gowin_emcu: add software support
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2022-01-23 11:20:44 +01:00 |
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Ilia Sergachev
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3f2a7b9bfd
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software/bios: set attribute used on main to fix optimization in some configurations
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2022-01-23 11:04:22 +01:00 |
|
Ilia Sergachev
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ef5f6398b2
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integration/builder: enable bios on gowin emcu
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2022-01-23 11:02:36 +01:00 |
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enjoy-digital
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0e9e57c926
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Merge pull request #1176 from Icenowy/gwpsram
gowin: add hack for copackaged PSRAM
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2022-01-23 08:33:29 +01:00 |