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1691 Commits

Author SHA1 Message Date
Florent Kermarrec aac16a9e11 add test_MigIo.py for de0_nano and de1 example 2012-09-13 13:18:03 +02:00
Florent Kermarrec 619671ad73 fix write function 2012-09-13 13:15:05 +02:00
Florent Kermarrec 8e86be1a6a add address parameter to migIo 2012-09-13 13:14:27 +02:00
Florent Kermarrec f4369c917f add spi2Csr tools : Python Host & Arduino Uart<-->Spi bridge 2012-09-13 11:34:19 +02:00
Florent Kermarrec c7e2b0c43e examples/de1: use of MigIo 2012-09-12 22:20:07 +02:00
Florent Kermarrec fc6225273b add MigIo Class 2012-09-12 22:19:42 +02:00
Florent Kermarrec bb6045e279 update README 2012-09-12 18:09:12 +02:00
Florent Kermarrec af64beec53 examples/de1: fix top 2012-09-12 18:07:36 +02:00
Florent Kermarrec fb624fddc4 initialize de1 example 2012-09-12 17:56:36 +02:00
Florent Kermarrec 24b7ba8722 examples/de0_nano : add load cmd / change rst polarity 2012-09-12 16:53:08 +02:00
Sebastien Bourdeauducq c86dd3cbef Define clock domains instead of passing extra clocks as regular signals 2012-09-11 00:21:07 +02:00
Sebastien Bourdeauducq 5931c5eb59 Basic support for new clock domain and instance API 2012-09-10 23:47:06 +02:00
Florent Kermarrec 4a59b63151 Clean up 2012-09-09 23:46:26 +02:00
Florent Kermarrec 7a24ee7027 Wip de0_nano example 2012-09-09 23:27:51 +02:00
Florent Kermarrec 6b8dda03c6 Wip de0_nano example 2012-09-09 22:32:09 +02:00
Florent Kermarrec 1578c74895 Initialize de0_nano example 2012-09-09 21:18:09 +02:00
Florent Kermarrec b8eaf0906a Clean up 2012-09-09 20:51:15 +02:00
Florent Kermarrec 2092c5a138 add global tb, fix bugs 2012-09-09 20:38:01 +02:00
Florent Kermarrec 289d35b952 simplify registers mgnt 2012-09-09 14:37:55 +02:00
Florent Kermarrec 2abd7f664d add tb_RecorderCsr.py 
fixs in recorder.py
 2012-08-27 00:44:26 +02:00
Florent Kermarrec d34c877401 split migScope to trigger & recorder 2012-08-26 21:30:23 +02:00
Florent Kermarrec a99a902fef add vcd generator 2012-08-26 20:56:56 +02:00
Florent Kermarrec 97cca81e0c tb_TriggerCsr.py : use truth table generator for Sum Lut 2012-08-26 15:44:43 +02:00
Florent Kermarrec 68750445cd add truth table generator 2012-08-26 15:15:44 +02:00
Florent Kermarrec bf7864104a tb_spi2Csr: Add clk_ratio 
tb_spi2Csr: Add Read
spi2Csr : fixs
 2012-08-26 13:03:11 +02:00
Florent Kermarrec 2e54001fc1 - fix Spi2Csr mistakes 2012-08-25 23:29:23 +02:00
Florent Kermarrec b5a44f2e98 add sim: tb_Spi2Csr.py (skeleton, WIP) 2012-08-25 21:53:06 +02:00
Florent Kermarrec d14ffb9146 add sim: tb_TriggerCsr.py 2012-08-25 18:46:58 +02:00
Florent Kermarrec a7d85af25b use ram for Sum 2012-08-24 00:16:00 +02:00
Florent Kermarrec f4cac2c102 Add simulation skeleton 
Remove SRLC16E, will be replaced by distributed ram
 2012-08-22 23:59:00 +02:00
Florent Kermarrec 7dd51b3d92 new library spi2Csr (skeleton) 2012-08-13 01:02:38 +02:00
Florent Kermarrec f586b13d4b add register interface to Trigger 2012-08-12 21:17:17 +02:00
Florent Kermarrec 051e8ac570 simplify EdgeDetector 2012-08-12 19:42:25 +02:00
Florent Kermarrec 09bcfb0fa5 fix masks on EdgeDetector 2012-08-12 19:39:26 +02:00
Florent Kermarrec 68c451148a add Trigger 2012-08-12 19:30:27 +02:00
Florent Kermarrec 449466d5b7 rename Recorder --> Storage 
add Recorder
 2012-08-12 17:31:15 +02:00
Florent Kermarrec 18452c8193 add simple Sequencer 2012-08-12 16:04:52 +02:00
Florent Kermarrec d22101eaa1 add Readme 2012-08-12 14:41:17 +02:00
Florent Kermarrec db2d3418c3 add Readme 2012-08-12 14:38:49 +02:00
Florent Kermarrec dbb363f039 - init Repo 2012-08-12 14:21:30 +02:00
Sebastien Bourdeauducq 42d5e850fe framebuffer: disable debugger by default 2012-08-05 01:11:37 +02:00
Sebastien Bourdeauducq 5ef8d5f534 bios/dataflow: use freeze register 2012-08-04 23:39:29 +02:00
Sebastien Bourdeauducq a5d6ced181 asmicon: fix and simplify refresh grant logic 2012-08-04 22:59:21 +02:00
Sebastien Bourdeauducq ea4c214790 asmicon/bankmachine: respect SDRAM write-to-precharge specification 2012-08-04 22:49:43 +02:00
Sebastien Bourdeauducq 1451cad710 asmicon/multiplexer: correct read-to-write delay to prevent conflicts on the tag bus 2012-08-04 17:38:42 +02:00
Sebastien Bourdeauducq 274a00217e bios: asmiprobe command 
Because with reordering architectures come order-dependent intermittent bugs.
 2012-08-04 16:32:15 +02:00
Sebastien Bourdeauducq 855eec776d Add ASMIprobe core 2012-08-04 16:31:24 +02:00
Sebastien Bourdeauducq 6807dba8bc asmicon/bankmachine/selector: fix round-robin CE 2012-08-03 22:33:52 +02:00
Sebastien Bourdeauducq df2b653c67 asmicon/bankmachine: do not insert buffer when using _SimpleSelector 2012-08-03 22:11:16 +02:00
Sebastien Bourdeauducq 6078a4e6d0 tb/selector: use _SimpleSelector 2012-08-03 22:10:04 +02:00