67159349d6
soc/interconnect: remove axi_lite
...
axi_lite code was defining AXI4Lite signals and doing a AXI4Lite bridge to the
CSR bus when LiteX was not having proper AXI support. LiteX now has proper AXI
support and it also cover what axi_lite was doing: To create a AXILite to CSR
bus, user can create an AXILite2Wishbone bridge and then connect the CSR bus
directly to the wishbone bus as done in the others non-AXI SoC.
2019-05-11 09:12:20 +02:00
745d83a332
boards: add initial NeTV2 support (clocks, leds, dram, ethernet)
2019-05-10 18:55:40 +02:00
a49d170a6d
soc/integration/soc_sdram: simplify/fix main_ram_size computation using new databits value of the phy
2019-05-10 15:46:22 +02:00
7445b9e2e0
soc/integration/soc_core: allow user to defined internal csr/interrupts
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For some designs with different capabilities, we want to run the same software
and then have the CSRs/Interrupts defined to a specific location.
2019-05-10 11:05:34 +02:00
f333abcfcb
boards/targets: use new add_csr method
2019-05-09 23:50:43 +02:00
d76a2c7db2
tools/litex_sim: add uart csr (required when with_uart=False with new add_csr method)
2019-05-09 23:33:08 +02:00
b6be534cd6
soc/integration/soc_core: rework csr assignation/reservation
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Similar refactor than on interrupts. Adds a add_csr method but still
retro-compatible with old way to declare CSRs.
2019-05-09 23:32:22 +02:00
3f09af6d6e
boards/targets: declare ethmac interrupt with new add_interrupt method
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The previous way to define interrupt is still valid, but using add_interrupt
method will ease maintenance
2019-05-09 12:13:15 +02:00
2abb3e809c
Merge branch 'master' of http://github.com/enjoy-digital/litex
2019-05-09 11:57:19 +02:00
47dc87584f
integration/soc_core: rework interrupt assignation/reservation
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The CPUs can now reserve specific interrupts with reserved_interrupts property.
User can still define interrupts in SoCCore.interrupt_map (old way) or use
add_interrupt method. Interrupts specific to SoCCore internal modules are
allocated automatically on the remaining free interrupt ids.
Priority for the interrupts allocation:
- 1) CPU reserved interrupts.
- 2) User interrupts.
- 3) SoCCore interrupts.
2019-05-09 11:54:22 +02:00
3ee9ce0529
test/test_targets: fix test_ulx3s name
2019-05-09 11:48:57 +02:00
435cdad083
boards/targets: fix ulx3s/versa_ecp5 build
2019-05-09 11:48:32 +02:00
8caa38bc25
cpu: add `reserved_interrupts` property
2019-05-09 09:00:06 +02:00
c11eb4b51c
Merge pull request #179 from gsomlo/gls-xtra-addrlen
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soc/integration/cpu_interface: more arch-specific address size fixes
2019-05-09 08:57:31 +02:00
c264a00964
soc/integration/cpu_interface: more arch-specific address size fixes
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When generating arch-specific include files (generated/[mem|csr].h)
ensure address literal defines are suffixed by 'L', denoting their
'unsigned long' type. This inhibits compiler warnings when values
computed based on these constants are cast to pointers.
Also ensure csr_[read|write][b|w|l]() function declarations have
'unsigned long' address arguments.
Finally, restore the correct (32-bit, (unsigned *)) expected
behavior of the MMPTR() macro, inadvertently converted to an
arch-specific sized access (unsigned long *) by commit 5c2b8685
2019-05-08 16:03:36 -04:00
ff5179153c
boards/targets: make sys_clk_freq a parameter
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Most of the targets can now generate an abritrary sys_clk_freq from onboard XO.
2019-05-07 18:44:03 +02:00
a8cbe4ad84
boards/targets/minispartan6: for now revert experimental s6pll clocking
2019-05-07 13:05:28 +02:00
6fcbf10eb9
boards/plarforms/minispartan6: default to xc6slx25
2019-05-07 12:48:36 +02:00
b7e3713388
bios/boot/ update linux memory mapping
2019-05-07 11:59:28 +02:00
190ff89aaa
tools/litex_term: add json support to load images to memory, allow passing speed as float
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example json file (serialboot.json):
{
"binaries/Image": "0xc0000000",
"binaries/rootfs.cpio": "0xc2000000",
"binaries/rv32.dtb": "0xc3000000",
"emulator/emulator.bin": "0x20000000"
}
example command:
lxterm --images=serialboot.json /dev/ttyUSBX
2019-05-06 23:56:33 +02:00
a50aff2c74
Merge pull request #178 from daveshah1/vexriscv_linux_yosys
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vexriscv: Fix some floating signals
2019-05-04 20:02:42 +02:00
a048ba47c4
vexriscv: Fix some floating signals
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Signed-off-by: David Shah <dave@ds0.me>
2019-05-04 17:27:21 +01:00
fcd518b5d0
bios/boot: add specific flash_boot for linux with vexriscv
2019-05-04 11:27:01 +02:00
1ba1ad9a00
bios/boot: rename MM_RAM to EMULATOR_RAM
2019-05-03 19:47:36 +02:00
fbb24720f0
soc/get_mem_data: add direct support for regions
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We now support passing filename (offset=0), json file and regions
2019-05-03 13:24:06 +02:00
0714816f31
soc/interconnect/axi: add AXI2AXILite converter and use it in AXI2Wishbone
2019-05-03 11:59:06 +02:00
c6d0d23445
soc/interconnect/axi: add AXI Lite definition
2019-05-03 09:43:12 +02:00
9fab4752c4
soc/interconnect/axi: add comment on axi signas that are present but not used
2019-05-03 09:30:59 +02:00
5989076346
cores/cpu/vexriscv: add VexRiscvTimer and use it for the linux variant
2019-05-03 09:30:26 +02:00
21bf10383d
bios/boot: add liftoff banner just before booting
2019-05-02 18:26:35 +02:00
8f4685b3b1
bios/boot/netboot: only get boot.bin as default, add linux_vexriscv netboot config
2019-05-02 16:34:41 +02:00
6cf1ff091c
soc/interconnect/axi: connect axi.ar/aw when selecting write or read
2019-05-02 09:58:55 +02:00
6affc56a09
soc/interconnect/axi: wishbone address shift is not always 2, make it generic
2019-05-02 09:35:07 +02:00
698bc88296
soc/interconnect/wishbone: allow setting adr_width (default to 30)
2019-05-02 09:34:30 +02:00
4dccb8a9eb
soc/interconnect/axi/AXI2Wishbone: add buffer on axi command to be sure command is accepted before response is sent
2019-05-01 12:59:04 +02:00
9f8f0eb18e
build/sim: update tapcfg
2019-05-01 12:34:12 +02:00
2515c7b0b5
Merge pull request #176 from gsomlo/gls-ulong-addr
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software: use "unsigned long" for address values, also 8-byte alignment
2019-05-01 12:09:18 +02:00
5c2b8685fc
software: use "unsigned long" for address values, also 8-byte alignment
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Enable future support for 64-bit CPU models.
2019-04-29 15:03:38 -04:00
74d37465b3
test/test_targets: comment bad variant tests for now
2019-04-29 17:11:42 +02:00
5c1d980540
soc/interconnect/axi: add burst support to AXI2Wishbone
2019-04-29 16:49:20 +02:00
6de2713524
soc/interconnect/axi: add capabilities to AXIBurst2Beat and simplify/optimize
2019-04-29 14:02:05 +02:00
305b8879de
integration/soc_core: use cpu name as cpu-type for all cpus (mor1kx was instanciated with or1k)
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Keep or1k retro-compatibility for now but add a warning
2019-04-29 10:14:30 +02:00
4e50f36b72
build/tools: add deprecated_warning
2019-04-29 10:12:54 +02:00
b40d1b73c4
cpu_interface: default to gcc for all cpus unless told otherwise (mor1kx default was clang)
2019-04-29 10:00:04 +02:00
dbb71af189
cpu: use property methods to return name, endianness, gcc triple/flags, linker output format
2019-04-29 09:58:51 +02:00
d828c3a596
cpu: integrate nmigen version of Minerva, add submodule
2019-04-28 23:40:33 +02:00
2c3c6bdf9b
Updating documents from LiteX BuildEnv Wiki
2019-04-28 11:41:33 +02:00
bf27869ad9
fix vexriscv build
2019-04-28 11:10:20 +02:00
2d5bae3def
Merge pull request #175 from mithro/cpu-docs
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Standardizing `cpu_variants` and adding lots of documentation
2019-04-27 21:24:06 +02:00
5cbc5bc199
Adding testing of cpu variants.
2019-04-26 18:57:49 -05:00
Florent Kermarrec
Mateusz Holenko
Gabriel L. Somlo
David Shah
Kurt Kiefer
Tim 'mithro' Ansell