383c05e239
Merge pull request #240 from danielkucera/patch-1
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more understandable error when missing a memory
2019-08-13 10:34:50 +02:00
a5eaf172c5
more understandable error when missing a memory
2019-08-13 10:14:16 +02:00
1d957d7a31
Update .gitmodules
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http to https
2019-08-12 22:20:34 +08:00
2b815f7096
Merge pull request #235 from gsomlo/gls-trellis-yosys-opt
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build/lattice/trellis: use additional yosys optimization flags
2019-08-10 15:33:05 +02:00
6c298cb708
build/lattice/trellis: use abc9 techmapping pass with yosys
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Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-08-09 09:12:22 -04:00
31bfb54667
software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys
2019-08-09 13:26:31 +02:00
e670cb9176
cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus
2019-08-09 12:33:10 +02:00
6d94c07d70
software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle
2019-08-09 10:33:42 +02:00
0c287b11ba
cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap
2019-08-09 09:27:32 +02:00
82cd557c24
software/bios: add Ethernet PHY MDIO read/write/dump commands
2019-08-09 09:26:41 +02:00
0ba9ab92b4
altera/common: fix AsyncResetSynchronizer polarity and simplify
2019-08-08 16:19:22 +02:00
124dff8f3f
build/xilinx/common: improve presentation
2019-08-08 16:08:55 +02:00
60873a5b73
microsemi/common: improve presentation
2019-08-08 16:06:40 +02:00
36d9d78c5e
build/altera/common: improve presentation
2019-08-08 16:02:34 +02:00
95953d2928
platforms/default_clk_period: use 1e9/freq
2019-08-07 08:36:04 +02:00
f1d8c70bd8
targets/minispartan6/crg: only keep S6PLL code
2019-08-07 08:29:59 +02:00
d3d0a6231c
cores/clock: juse use 1e9/freq instead of period_ns
2019-08-07 08:29:20 +02:00
a881817fb3
cores/clock/s6pll: add phase support
2019-08-07 08:18:54 +02:00
6b7ca0cff7
cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq
2019-08-07 08:17:44 +02:00
1884649de1
litex_term: make sure to unconfigure console when board is unplugged
2019-08-06 08:46:25 +02:00
e052d7f645
soc/integration/builder: -x
2019-08-06 07:56:45 +02:00
236070fdcf
cores: -x on spi.py
2019-08-05 10:36:43 +02:00
a9fe2788a2
wishbone/SRAM: make read_only emited verilog code compatible with all tools
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Quartus was not able to implement ROM correctly, see #228
2019-08-05 09:08:56 +02:00
ce5c58592b
soc/cores/uart: add FT245 FIFO mode support (sync & async)
2019-08-04 12:22:35 +02:00
a496760cb6
build/altera/quartus: use .bat on win32/cygwin
2019-08-02 10:27:38 +02:00
7e0ea07076
build/xilinx/vivado: change severity of Common 17-55 critical warning to warning
2019-08-01 21:03:05 +02:00
92d93ad221
cores/pwm: remove default CSR reset values.
2019-07-29 08:38:28 +02:00
25ca0a8b71
soc: generate git header and show migen/litex git sha1 in bios
2019-07-27 20:27:53 +02:00
ae00482dde
Merge pull request #223 from sergachev/master
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support vivado incremental implementation
2019-07-25 20:24:25 +02:00
fdb119cb7b
support vivado incremental implementation
2019-07-25 19:18:11 +02:00
e637aa657b
Merge pull request #222 from antmicro/bump_vexriscv
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cpu/vexriscv: bump submodule
2019-07-25 09:25:26 +02:00
932475a29b
cpu/vexriscv: bump submodule
2019-07-25 08:43:35 +02:00
bc7ab637dd
bios/sdram: fix compilation warning
2019-07-25 07:46:14 +02:00
a7895e4982
test/test_axi: remove use of rand_wait, rename rand_level to random
2019-07-23 21:02:09 +02:00
1cfb36e1e4
soc_core: round memory regions size/length to next power of 2 (if not already a power of 2)
2019-07-23 20:35:28 +02:00
556d2c7c0f
Merge pull request #221 from antmicro/bump_vexriscv
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cpu/vexriscv: bump submodule
2019-07-23 12:01:13 +02:00
3e89c56468
cpu/vexriscv: bump submodule
2019-07-23 11:49:18 +02:00
e673fce445
bios/boot: fix default EMULATOR_RAM_BASE
2019-07-23 10:28:19 +02:00
0acacbaa82
cores/clock: cleanup
2019-07-23 09:54:30 +02:00
edf8aa8cfd
cores/clock: add initial iCE40 support
2019-07-23 09:27:20 +02:00
6d54335839
cores/spi_flash/add_clk_primitive: return if clk primitive is not needed
2019-07-22 21:55:07 +02:00
462d12bacc
bios/boot: define EMULATOR_RAM_BASE if not defined, add KERNEL_IMAGE_RAM_OFFSET
2019-07-22 21:54:24 +02:00
fc12961e7e
soc_core: fix cpu_variant definition
2019-07-22 12:46:39 +02:00
af61688d1d
bios/boot: fix booting rework
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- keep emulator.bin in a specific ram (for now)
- print message when falling back to boot.bin
- print destination on tftp download (to ease debug)
2019-07-22 11:47:41 +02:00
4b686dbdb2
soc_core: fix cpu_variant config (we don't want the extension)
2019-07-22 11:44:32 +02:00
7d9cf1d2bd
Merge pull request #216 from antmicro/booting_vexriscv_linux
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Rework booting Linux on VexRiscv
2019-07-22 11:44:20 +02:00
95cfd0b9e5
cores/spi_flash: add SpiFlashCommon and use it to add clk primitives (7-Series/ECP5 support for now)
2019-07-22 10:28:03 +02:00
bfdcf4b2a0
platforms/versa_ecp5: add spiflash pads
2019-07-22 10:25:55 +02:00
41eb21b343
soc_core: optimize mem_decoder
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Non-optimized version was tested on 7-series and was additional resource usage
was not noticeable. This does not seems to be the case on iCE40 (see #220 ), so
hand optimize it. On 256MB aligned addresses, it should be equivalent to the
old decoder used by previously in LiteX.
The only requirement is that to have address aligned on size, which was already
the case. An assertion will trigger it this condition is not respected.
2019-07-22 08:53:54 +02:00
0eff65bb31
cores/up5ksram: optimize bus.adr decoding
2019-07-22 07:55:47 +02:00
enjoy-digital
Daniel Kucera
atommann
Gabriel L. Somlo
Ilia Sergachev
Mateusz Holenko