Commit Graph

3306 Commits

Author SHA1 Message Date
Florent Kermarrec da13bd536e gensoc: add csr_data_width and csr_address_width as parameters In some case we want to have mode than 32 CSR or and csr_data_width != 8 2015-02-14 03:24:23 -08:00
Florent Kermarrec 452c60e0c3 endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations) 2015-02-14 03:10:56 -08:00
Florent Kermarrec 319465445d actorlib/structuring: fix eop generation in Pack 2015-02-14 03:07:18 -08:00
Sebastien Bourdeauducq d51d33af73 mibuild: make resolve_signals public 2015-02-14 03:05:07 -08:00
Florent Kermarrec beef7425ce mibuild: return verilog namespace with build 2015-02-14 03:02:47 -08:00
Florent Kermarrec c7eba8f4c4 remove crc since each crc is specific. It's probably better to adapt code for each case. 2015-02-14 03:01:12 -08:00
Florent Kermarrec 3559de9b4c add setup.py 2015-02-14 02:44:39 -08:00
Florent Kermarrec d3cf2594f2 update download instructions 2015-02-12 22:03:24 +01:00
Florent Kermarrec b64dba7a81 update download instructions 2015-02-12 22:03:04 +01:00
Florent Kermarrec aedc964908 update download instructions 2015-02-12 22:02:50 +01:00
Florent Kermarrec 04f7fbd7e2 simplify litescope export with do_exit call and remove automatic clean 2015-02-12 21:15:51 +01:00
Florent Kermarrec f8003c92aa simplify litescope export with do_exit call and remove automatic clean 2015-02-12 21:04:52 +01:00
Florent Kermarrec 4e4800e1b2 simplify litescope export with do_exit call 2015-02-12 21:00:45 +01:00
Florent Kermarrec 61d12a3431 fix transport_rx_description (detected with new Migen check) 2015-02-12 20:45:15 +01:00
Florent Kermarrec bceee36ef6 etherbone: reads OK on hardware 2015-02-12 15:50:07 +01:00
Florent Kermarrec 23c4f5c090 etherbone: writes OK on hardware 2015-02-12 13:15:30 +01:00
Florent Kermarrec bfb50e698f etherbone: add more debug signals 2015-02-12 12:33:10 +01:00
Florent Kermarrec 0818c29287 etherbone: probing OK on hardware 2015-02-12 12:17:17 +01:00
Florent Kermarrec b6aeea676b etherbone: simplify model usage 2015-02-12 12:09:39 +01:00
Florent Kermarrec a2455b19af etherbone: create example design target 2015-02-12 11:37:54 +01:00
Florent Kermarrec f03212a30d cosmetic: define params before payload 2015-02-12 11:10:05 +01:00
Florent Kermarrec 9eb2e313e7 etherbone_tb: add autocheck 2015-02-12 02:00:26 +01:00
Florent Kermarrec d5887416f1 code cleanup 2015-02-12 01:30:17 +01:00
Florent Kermarrec b8f2fc2290 move generic modules to generic/__init__.py 2015-02-12 01:19:36 +01:00
Florent Kermarrec e4958ffab3 etherbone: cleanup 2015-02-12 01:12:52 +01:00
Florent Kermarrec ea47037570 etherbone_tb OK (will need cleanup) 2015-02-12 00:01:03 +01:00
Florent Kermarrec fca89e8b74 etherbone: wishbone reads seems OK in simulation 2015-02-11 21:51:25 +01:00
Florent Kermarrec 4a4e82b5f6 etherbone: wishbone writes seems OK in simulation 2015-02-11 20:54:32 +01:00
Florent Kermarrec eee07e6eec etherbone: code wishbone master 2015-02-11 19:44:02 +01:00
Florent Kermarrec 384fc3c868 etherbone: record wip 2015-02-11 18:37:59 +01:00
Florent Kermarrec abe6d87438 etherbone: add record depacketizer/packetizer (wip) 2015-02-11 16:21:06 +01:00
Florent Kermarrec 247c30ae26 etherbone: add etherbone_tb, able to probe etherbone endpoint 2015-02-11 14:33:17 +01:00
Florent Kermarrec a2279bd2fa models: use .format everywhere 2015-02-11 11:28:15 +01:00
Florent Kermarrec 227fc4f5e5 etherbone: cleanup model 2015-02-11 11:11:54 +01:00
Florent Kermarrec 02bfc0a5a8 etherbone: clean up ohwr dissector, Python model checked against it 2015-02-10 23:05:36 +01:00
Florent Kermarrec 5728f61f3a etherbone: add model skeleton 2015-02-10 22:45:10 +01:00
Florent Kermarrec 1de3bccfc8 etherbone: add dissector from ohwr.org 2015-02-10 18:43:14 +01:00
Florent Kermarrec 31bdc48a57 etherbone: wip 2015-02-10 16:43:31 +01:00
Florent Kermarrec 310040b43b test_udp: test loopback on port 6000 (dw=8) and port 8000 (dw=32) OK on board! 2015-02-10 16:30:34 +01:00
Florent Kermarrec 974169218f targets/udp: create udp loopback on port 8000 with dw=32 (to test data_width converters) 2015-02-10 16:24:45 +01:00
Florent Kermarrec 92904330f7 phy: add hw_init_reset (useful when used without CPU) 2015-02-10 16:03:07 +01:00
Florent Kermarrec 000ba7f0ab create Port class and remove connect method of mac/ip/udp Ports 2015-02-10 15:37:29 +01:00
Florent Kermarrec 01d980b062 move more things to common files 2015-02-10 15:22:06 +01:00
Florent Kermarrec 3187a93984 generic: add crossbar and use it in mac/ip/udp 2015-02-10 15:16:35 +01:00
Florent Kermarrec f0993ea422 README: use migen fork for now 2015-02-10 11:28:59 +01:00
Florent Kermarrec 9f91348c1c udp/crossbar: add possibility to get port with dw != 8 (16, 32, 64, ...) 2015-02-10 11:22:23 +01:00
Florent Kermarrec 4e8e1dd8b1 use new Migen feature: payload_layout/param_layout 2015-02-10 10:30:39 +01:00
Florent Kermarrec 6b0e525b8c make packetizer/depacketizer more generic (remove width limitation) 2015-02-10 09:25:36 +01:00
Florent Kermarrec 2063205a9e doc: init 2015-02-09 23:26:27 +01:00
Florent Kermarrec ab322066ec etherbone: add skeleton 2015-02-09 22:37:41 +01:00