Florent Kermarrec
|
6a4e3bb5c0
|
build/xilinx/vivado: use build_name as top in synth_design
|
2015-12-09 11:40:27 +01:00 |
|
Florent Kermarrec
|
3191533889
|
soc/software/libnet: add debug defines on microudp
|
2015-12-07 12:03:36 +01:00 |
|
Florent Kermarrec
|
4fed1cc7a7
|
soc/integration/builder: move csr_csv generation outside of generate include
we mostly use csr_csv for designs without CPU
|
2015-12-03 15:16:22 +01:00 |
|
Florent Kermarrec
|
90f03133ef
|
build/sim/verilator: add toolchain_path parameter
|
2015-12-02 15:35:55 +01:00 |
|
Florent Kermarrec
|
e8262ed447
|
build: pass build_name to get_verilog (same name for top module and top level file)
|
2015-12-02 14:18:09 +01:00 |
|
Florent Kermarrec
|
b7a1888a36
|
gen/fhdl/verilog: add regular comb parameter to allow implementation of simulation code (for icarus)
We will remove that when we will be using new migen simulator
|
2015-12-02 14:16:23 +01:00 |
|
Florent Kermarrec
|
646d3b19b4
|
boards/nexys_video: use ethernet constraints similar to kc705
|
2015-12-01 11:50:05 +01:00 |
|
Florent Kermarrec
|
ca6b9aa6e3
|
boards/targets: add default rom/ram configuration for arty
|
2015-12-01 10:20:16 +01:00 |
|
Florent Kermarrec
|
e5d35ccb6d
|
boards/targets: add nexys_video
|
2015-12-01 10:19:41 +01:00 |
|
Florent Kermarrec
|
4bfd1fdce6
|
boards/plaforms: fix IOStandard of eth_rst_n
|
2015-11-30 22:27:40 +01:00 |
|
Florent Kermarrec
|
b6a6b5d540
|
boards/platforms: add cpu_reset to nexys_video and some fixes around DDR3
|
2015-11-30 21:53:01 +01:00 |
|
Florent Kermarrec
|
5694dca0fc
|
boards/platforms: add hdmi_in/hdmi_out/ethernet/dram to nexys_video
|
2015-11-30 20:46:57 +01:00 |
|
Florent Kermarrec
|
7e1df951ba
|
boards/platforms: add nexys_video (basic)
|
2015-11-30 20:25:00 +01:00 |
|
Florent Kermarrec
|
a716c562f0
|
gen/build: use name_override for all IOs defined in Platform file (avoid random naming of IOs)
|
2015-11-30 18:26:33 +01:00 |
|
Florent Kermarrec
|
53c86e34f4
|
build: ensure we return to working directory after building
|
2015-11-30 13:33:39 +01:00 |
|
Florent Kermarrec
|
f6aeb6e41a
|
soc/interconnect/stream: improve Pipeline to allow passing endpoints
|
2015-11-28 18:31:47 +01:00 |
|
Florent Kermarrec
|
d85d2b7b9b
|
soc/interconnect/stream_packet: add check of field's width vs signal's width in Header.get_field
|
2015-11-27 20:14:01 +01:00 |
|
Florent Kermarrec
|
c0539fff3e
|
boards: add new digilent arty
|
2015-11-27 00:29:30 +01:00 |
|
Florent Kermarrec
|
c24727ab4c
|
soc/integration: allow using builder with soc.cpu_type == None
|
2015-11-26 17:44:50 +01:00 |
|
Florent Kermarrec
|
7298fff1e6
|
soc/interconnect/stream_packet: fix Counter removing
|
2015-11-24 20:30:53 +01:00 |
|
Florent Kermarrec
|
8ebffc563a
|
soc/tools/remote/csr_builder: manage memory regions and some fixes on CSRRegister
|
2015-11-23 19:13:37 +01:00 |
|
Florent Kermarrec
|
254504e73f
|
soc/integration/builder: export constants and memory_regions with csr_csv
|
2015-11-23 19:12:58 +01:00 |
|
Florent Kermarrec
|
f6a2d5847a
|
soc/tools/remote/client: make csr_csv parameter optional and default value to None
|
2015-11-23 18:39:28 +01:00 |
|
Florent Kermarrec
|
6f4dd14ffa
|
soc/software/boot: add #ifndef on LOCALIP and REMOTEIP to allow definition in the SoC with add_constant
|
2015-11-23 11:08:04 +01:00 |
|
Florent Kermarrec
|
cb22a207f1
|
build/generic_platform: add support for int parameter for Pins (useful for core generation)
|
2015-11-19 14:57:09 +01:00 |
|
Florent Kermarrec
|
8056653004
|
soc/tools/remote/server: add --debug parameter
|
2015-11-17 15:43:10 +01:00 |
|
Florent Kermarrec
|
6870707620
|
soc/tools/remoter/server: fix exit on KeyboardInterrupt
|
2015-11-17 15:31:23 +01:00 |
|
Florent Kermarrec
|
8ff31557c6
|
soc/tools/remoter/server: add some printfs
|
2015-11-17 15:18:46 +01:00 |
|
Florent Kermarrec
|
1a92489555
|
soc/tools/remote: add comm_pcie and comm_udp (to be tested)
|
2015-11-17 15:07:00 +01:00 |
|
Florent Kermarrec
|
d6fdd76930
|
soc/tools/remote: small cleanup and remove csr_data_width from server side
|
2015-11-17 11:35:22 +01:00 |
|
Florent Kermarrec
|
71483b8935
|
soc/tools: initialize wishbone remote control (for now only uart)
|
2015-11-17 01:05:52 +01:00 |
|
Florent Kermarrec
|
1cde84dccf
|
soc/cores/uart remove software (will be re-written and will move to soc/tools)
|
2015-11-16 17:07:22 +01:00 |
|
Florent Kermarrec
|
1f80bb9561
|
soc/interconnect/stream_packet: remove Counter
|
2015-11-16 16:53:23 +01:00 |
|
Florent Kermarrec
|
ec35290c45
|
soc/interconnect/wishbonebridge: remove Counter
|
2015-11-16 16:48:37 +01:00 |
|
Florent Kermarrec
|
6fd0b73817
|
build: remove edif support
|
2015-11-16 16:26:38 +01:00 |
|
Florent Kermarrec
|
e407a1cdda
|
gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal and blocking_assign
|
2015-11-16 16:18:09 +01:00 |
|
Florent Kermarrec
|
2f52d364af
|
soc/interconnect/stream/SyncFIFO: expose fifo level
|
2015-11-16 16:11:31 +01:00 |
|
Florent Kermarrec
|
7ed2576ce1
|
soc/integration/cpu_interface: add bases, constants and memories output to csv files
|
2015-11-15 00:04:44 +01:00 |
|
Florent Kermarrec
|
af909b43d5
|
soc/cores/uart: add UARTWishboneBridgeDriver software
|
2015-11-14 21:23:20 +01:00 |
|
Florent Kermarrec
|
3a2e6117f4
|
soc/interconnect/stream: add Cast and others small fixes
|
2015-11-14 12:17:09 +01:00 |
|
Florent Kermarrec
|
041483dbe1
|
soc/integration/builder: only copy Makefiles when not using symlinks
|
2015-11-14 03:36:46 +01:00 |
|
Florent Kermarrec
|
a2aa5726bf
|
soc/cores: remove liteeth_mini and use liteeth
|
2015-11-14 03:22:43 +01:00 |
|
Florent Kermarrec
|
16ba646b1b
|
add TODOs
|
2015-11-14 03:15:10 +01:00 |
|
Florent Kermarrec
|
cf4c7da2e7
|
fix soc/integration/soc_core.py
|
2015-11-14 02:44:12 +01:00 |
|
Florent Kermarrec
|
032f5a9620
|
soc/interconnect: add stream_sim
|
2015-11-14 00:43:49 +01:00 |
|
Florent Kermarrec
|
ba959c832d
|
soc/interconnect: rename packet to stream_packet
|
2015-11-14 00:42:58 +01:00 |
|
Florent Kermarrec
|
1158b98fdd
|
doc: update logo
|
2015-11-13 23:40:27 +01:00 |
|
Florent Kermarrec
|
fc3ffe87ac
|
for now use our fork of migen (to be able to simulate our designs)
|
2015-11-13 18:31:46 +01:00 |
|
Florent Kermarrec
|
ae3d54499a
|
litex/gen: reintegrate migen with modifications to be able to simulate with vpi until all missing features of the new simulator are implemented
|
2015-11-13 14:44:16 +01:00 |
|
Florent Kermarrec
|
7d6cee6751
|
soc/interconnect/stream: add BufferizeEndpoints
|
2015-11-12 18:54:15 +01:00 |