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9242 Commits

Author SHA1 Message Date
Florent Kermarrec 6c6c238309 cpu/gowin_emcu: Switch to LiteX's UART (Using integrated UART is not really useful for now and make things less flexible, ie no UARTBone/Crossover possibilities). 2024-01-04 11:29:12 +01:00
Florent Kermarrec 6a6837062a cpu/gowin_emcu: Remove interrupt signal since not yet functional/used. 2024-01-04 10:40:47 +01:00
Florent Kermarrec 386854cbd3 cpu/gowin_emcu: Use crt0.c from cortex_m3. 2024-01-04 10:38:45 +01:00
Florent Kermarrec de6fbf1271 cpu/gowin_emcu: Directly connect AHB interfaces, using for loops make things unclear/difficult to follow. 2024-01-04 10:33:50 +01:00
Florent Kermarrec b0cde1acdd cpu/gowin_emcu: Switch SRAM to 4 SRAMS of 8-bit each. 2024-01-04 10:12:36 +01:00
Florent Kermarrec 01520cd638 cpu/gowin_emcu: Simplify SRAM. 2024-01-04 09:59:17 +01:00
Florent Kermarrec 6d3c955d59 cpu/gowin_emcu: Increase similarities with cortex_m3 (since gowin_emcu is a Cortex M3). 2024-01-04 09:09:18 +01:00
Florent Kermarrec 85ef3bd8a7 cpu/gowin_emcu: Add missing reset signals. 2024-01-03 19:41:03 +01:00
Florent Kermarrec 3f9de470f6 cpu/gowin_emcu: Add gcc_flags method and set UART_POLLING in it. 2024-01-03 19:15:46 +01:00
Florent Kermarrec 456dda050c cpu/gowin_emcu: Cleanup/Simplify. 2024-01-03 19:11:05 +01:00
Florent Kermarrec 3909b1d611 build/openfpgaloader: Add kwargs support to flash method and some comments. 2024-01-02 13:50:02 +01:00
gsomlo acf07a21c9
soc: fix typo in cpu mem_bus axi-via-wb downconvert (#1865) 
Fixes: 002aad7a4

Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2024-01-01 13:32:40 -05:00
enjoy-digital 56f61986f0
Merge pull request #1862 from dau-dev/tkp/classifiers 
Fix classifiers to satisfy format checks
 2023-12-31 19:17:43 +01:00
Tim Paine 68cfb6eea0 Fix classifiers to satisfy format checks 2023-12-28 15:49:31 -05:00
Florent Kermarrec 67cfcadf79 setup.py/CHANGES.md: Prepare 2023.12 release. 2023-12-25 15:36:10 +01:00
Gwenhael Goavec-Merou 7062e3379f build/efinix/ifacewriter: bypass clks out frequency check for Trion when a feedback clock is used 2023-12-20 20:33:15 +01:00
Gwenhael Goavec-Merou 54c58ef8b9 build/efinix/ifacewriter: reorder FEEDBACK for Trion devices. 2023-12-20 20:29:23 +01:00
Gwenhael Goavec-Merou 7d5de90a24 soc/cores/clock/efinix: remove 2 output clocks limit, reset o_div_max when a nex vco_max_freq is found 2023-12-20 20:28:51 +01:00
Florent Kermarrec 040b554022 CHANGES.md: Update. 2023-12-20 16:11:12 +01:00
Florent Kermarrec 23fbd1b334 CHANGES.md: Update. 2023-12-20 16:10:03 +01:00
Florent Kermarrec 4721029e58 CHANGES.md: Update. 2023-12-20 15:25:14 +01:00
Florent Kermarrec fadea1d31b CHANGES.md: Update. 2023-12-20 08:08:42 +01:00
Gwenhael Goavec-Merou cd503bc9af build/efinix/ifacewriter: Titanium PLL's feedback clock 2023-12-19 21:25:59 +01:00
Florent Kermarrec 048c42820c setup.py: Switch minimum Python version to 3.7 (To allow more than 255 arguments in functions). 2023-12-19 10:32:12 +01:00
Florent Kermarrec 33c07a094e setup.py: Specify UTF-8 encoding for long_description/README.md. 2023-12-19 10:16:15 +01:00
Florent Kermarrec 0c3cda3ee8 CHANGES.md: Update. 2023-12-19 10:09:44 +01:00
Florent Kermarrec 2318ff37d2 setup.py: Improve indentation. 2023-12-19 10:08:40 +01:00
Florent Kermarrec b6e89c646e CHANGES: Update. 2023-12-14 11:08:55 +01:00
Gwenhael Goavec-Merou 84e376efcb build/openocd: jtagstream_rxtx reduce tx to 16 and rx to 128 2023-12-13 15:08:18 +01:00
enjoy-digital cdd80a5f4f
Merge pull request #1433 from tpwrules/faster-jtaguart 
Increase JTAG UART upload speed
 2023-12-13 15:05:37 +01:00
enjoy-digital 5dac2fc16f
Merge pull request #1852 from trabucayre/increase_cmd_timeout_delay 
soc/software/bios/boot: serialboot: increase CMD_TIMEOUT_DELAY
 2023-12-13 14:39:17 +01:00
Gwenhael Goavec-Merou 00b94a5512 soc/software/bios/boot: serialboot: increase CMD_TIMEOUT_DELAY 2023-12-13 14:29:54 +01:00
Florent Kermarrec faae1ea95a integration/soc/jtag: Switch JTAGPHY to sys_clk/simplify. 2023-12-13 09:24:23 +01:00
Florent Kermarrec 4e57cca85f cpu/vexriscv: Cleanup reset. 2023-12-13 09:17:15 +01:00
Florent Kermarrec f2c5ff376c soc/cores/jtag: Switch to stream.ClockDomainCrossing and use common_rst. 2023-12-13 09:16:55 +01:00
Gwenhael Goavec-Merou 94eca8628c Revert "soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width" 
This reverts commit 6d34b8ed87.
 2023-12-12 15:19:16 +01:00
Gwenhael Goavec-Merou 6d34b8ed87 soc/integration/soc: add_sdram, remove litedram_wb and converter: let LiteDRAMWishbone2Native dealing with addr/data width 2023-12-12 12:05:47 +01:00
Gwenhael Goavec-Merou 08ff003178 tools/litex_server.py: jtag/udp mode: add missing addr_width parameter 2023-12-09 06:08:53 +01:00
Gwenhael Goavec-Merou c1871eaf42 soc/integration/soc: add_jtagbone: pass address_width to UARTBone constructor 2023-12-09 06:07:58 +01:00
Florent Kermarrec acd66f1346 soc/bus_addressing_convert: Fix s2m adaptation case, the 2 adaptation cases were swapped. 2023-12-08 15:25:30 +01:00
Florent Kermarrec 8d6120c476 CHANGES: Update. 2023-12-08 12:11:37 +01:00
enjoy-digital 1e5df2dedf
Merge pull request #1851 from trabucayre/add_64_bus_support_v2 
Add AXI/AXILite 64 bus support
 2023-12-08 12:08:09 +01:00
Gwenhael Goavec-Merou 2134c0d0b0 soc/integration/soc: when adding a CSR Bridge bus_bridge must keep bus.address_width instead of the default value 2023-12-08 12:02:45 +01:00
Gwenhael Goavec-Merou 1a8fd2e808 soc/interconnect/axi/axi_full: AXIInterconnectShared, AXICrossbar: propagate master bus address width to Interface 2023-12-08 12:00:50 +01:00
Gwenhael Goavec-Merou 13987659a9 soc/interconnect/axi/axi_lite: AXILiteInterconnectShared, AXILiteCrossbar: propagate master bus address width to Interface 2023-12-08 11:59:33 +01:00
Gwenhael Goavec-Merou 01ce8ab0d1 soc/interconnect/axi/axi_lite:axi_lite_to_simple: avoid multiple read access 2023-12-08 11:57:35 +01:00
Florent Kermarrec afaeca98ce CHANGES.md: Update. 2023-12-07 16:33:32 +01:00
enjoy-digital 1512080527
Merge pull request #1850 from trabucayre/efinix_serdes 
Efinix PLL calc when feedback != INTERNAL
 2023-12-07 15:05:57 +01:00
Gwenhael Goavec-Merou 491a207a37 soc/cores/clock/efinix: calc PLL parameters for Trion when feedback != INTERNAL 2023-12-07 12:08:28 +01:00
Gwenhael Goavec-Merou 08a62d4b5f build/efinix/ifacewriter: PLL feedback for Trion 2023-12-06 16:58:50 +01:00