d0dc5c8d95
CHANGES: Update.
2022-02-17 10:36:05 +01:00
55a790308f
cores/bitbang: Add TODO.
2022-02-04 09:01:00 +01:00
8baf5cacc1
CHANGES: Update.
2022-02-02 12:05:46 +01:00
1c5d91dce1
cores/jtag: Deprecate JTAG Atlantic support (Advantageously replaced by JTAG-UART).
2022-02-01 11:19:36 +01:00
6f6a10db5c
CHANGES: Update.
2022-01-31 17:00:51 +01:00
e8be391504
setup.py: Deprecate lxterm/lxserver/lxsim short names.
...
These were no longer really used and was confusing.
2022-01-26 15:14:54 +01:00
681f474c66
CHANGEs: Update.
2022-01-20 09:25:49 +01:00
02fe32bd79
tools/litex_server/sim: Deprecate bridge use in favor of crossover (was already supported).
2022-01-19 16:54:56 +01:00
fda3164be4
soc/add_uart: Separate name/uart_name to allow multiple UARTs in the same design.
2022-01-19 15:48:42 +01:00
2f433611dd
litex_sim: Add .json support for --rom/ram/sdram-init.
2022-01-19 09:58:38 +01:00
0eded56afa
CHANGES: Start listing changes since 2021.12.
2022-01-17 10:17:10 +01:00
3fde251216
CHANGES: Set release date.
2022-01-05 08:53:10 +01:00
f04a3dcc50
CHANGES: List changes since 2021.08.
2022-01-03 19:29:05 +01:00
beb7cc691d
CHANGES: Do 2021.08 release.
2021-09-15 15:05:47 +02:00
05b960d09b
CHANGES: Update.
2021-09-15 12:08:30 +02:00
a064e9d048
soc/interconnect/wishbone: Fix SEL propagation on UpConverter (thanks @Dolu1990).
2021-06-02 10:46:53 +02:00
d0e8de077c
soc/SoCController: Add separate fields for SoC and CPU resets.
...
As discussed in #909 , in some specific cases, it can be interesting to be able
to keep the CPU in reset while the rest of the SoC is still operating (ex the
peripherals/bridges).
With theses changes, the old behaviour is preserved to do a full SoC Reset (at
the exception that writing a 1 is now mandatory) and a separate field specific
to the CPU reset is added.
The SoC Reset is a pulse (otherwise the system would be stuck in Reset) while
the CPU Reset is based on the register value (so can be pulse or hold).
2021-05-17 11:43:04 +02:00
78bdde0424
cpu/vexriscv: Simplify CFU integration, use Cfu.v as default CFU when not specified and rename argument to --cpu-cfu.
2021-05-17 10:02:58 +02:00
87bb10f43b
CHANGES: Start listing changes for next release.
2021-05-17 09:58:46 +02:00
d6084cd1f9
CHANGES: Add 2021.04 changes.
2021-05-03 11:59:42 +02:00
737952577b
Changes: update/release.
2020-12-30 16:49:15 +01:00
3e115a0ecb
CHANGES: update.
2020-12-30 09:06:36 +01:00
5b4e4a3b4a
CHANGES: update.
2020-10-30 15:41:36 +01:00
a2b71fde4a
soc: change default CSR bus data-width to 32.
...
A CSR bus data-width of 32 has been validated on very various design and is
now recommended. It provides better performance without impacting resource
usage (even on iCE40).
2020-10-07 16:38:49 +02:00
b84a858b2c
CHANGES: initialize changes since last release.
2020-10-01 11:46:43 +02:00
0696b409ab
CHANGES: update.
2020-07-28 18:37:23 +02:00
8337039915
CHANGES: update.
2020-07-23 18:02:58 +02:00
8f92034ddd
CHANGES: update.
2020-07-22 23:10:26 +02:00
52b51e1e98
CHANGES: update.
2020-06-23 12:50:20 +02:00
68d3804cdb
CHANGES: update.
2020-06-11 19:25:16 +02:00
f9b43c81cc
software/liblitesdcard: switch to FatFs for sdcardboot.
2020-06-05 21:20:19 +02:00
10ff9d765f
CHANGES: update and change added features order.
2020-06-02 15:05:46 +02:00
68f83cbcaf
CHANGES: document deprecated/moved modules.
2020-05-27 18:46:55 +02:00
2934c085ef
CHANGES: add JTAG UART.
2020-05-27 09:00:43 +02:00
da7fd30847
CHANGES: update.
2020-05-23 18:56:51 +02:00
d4f44597de
CHANGES: update.
2020-05-14 09:34:37 +02:00
07e0153bb1
CHANGES: update.
2020-05-04 09:59:01 +02:00
10371a33f9
CHANGES: update.
2020-05-01 20:13:05 +02:00
d3e3ca0618
CHANGES: start listing changes for next release.
2020-05-01 19:07:43 +02:00
56aa7897df
create first release, add CHANGES and note about Python modules in README.
2020-04-28 11:36:44 +02:00
Florent Kermarrec