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9522 Commits

Author SHA1 Message Date
Florent Kermarrec 72854b8bef soc/integration/soc: Move adding constant for identifier directly to add_identifier method. 2024-05-30 09:19:24 +02:00
enjoy-digital d9332da433
Merge pull request #1973 from motec-research/dts_schema_compliance 
Dts schema compliance
 2024-05-30 09:16:01 +02:00
enjoy-digital f8cee3836d
Merge pull request #1972 from motec-research/dts_all_soc_sys_clk 
tools/litex_json2dts_linux: add all soc sys_clk
 2024-05-30 09:14:11 +02:00
Gwenhael Goavec-Merou 03e0f0d9a8 build/microsemi/libero_soc.py: replaced tabs by spaces 2024-05-30 08:57:59 +02:00
CLappin 72cade55da
Applying updates for Libero SoC support (#1855) 
* Updated the new_project tcl function and removed set_device function.

* fixing tcl command set_root and adding in build_hierarchy command.

* Adding tcl command to export_prog_job file for FPExpress, saves in Libero SoC default location.

* Attempting error checking on Libero SoC installation, and typo clean up.

* Fixing -adv_options in new_project tcl command.

* Moving script_ext back to its original location.

* Commented out Libero environment variable.

* Removed Libero environment variable.
 2024-05-30 08:56:27 +02:00
Gwenhael Goavec-Merou 94e6bb0247 CHANGES.md: updated for eos_s3 and quicklogic f4pga toolchain 2024-05-30 08:46:42 +02:00
Gwenhael Goavec-Merou 845e20c653 build/quicklogic/f4pga.py: fix Makefile, added a note for futur rework and link to toolchain install's instructions 2024-05-30 08:43:41 +02:00
Andrew Dennison 5e0c3f0a04 tools/litex_json2dts_linux: add compatible, model 
Fixes these dt-schema validation errors:
/: 'compatible' is a required property
	from schema $id: http://devicetree.org/schemas/root-node.yaml#
/: 'model' is a required property
	from schema $id: http://devicetree.org/schemas/root-node.yaml#
 2024-05-30 16:18:11 +10:00
Andrew Dennison 8a0d50b03e tools/litex_json2dts_linux: add all soc sys_clk 
Adds clocks for a downstream iclink soc, for example
when builder.add_json() has imported soc clocks.

Node names are as per devicetree fixed-clock.yaml bindings.
 2024-05-30 16:18:11 +10:00
Andrew Dennison ddc521b033 tools/litex_json2dts_linux: fix tlb-split 
This is also relevant to vexriscv_smp, not rocket specific.

Fixes these dt-schema validation errors:

cpus: cpu@0: 'tlb-split' is a dependency of 'd-tlb-size'
	from schema : http://devicetree.org/schemas/cpus.yaml#
cpus: cpu@0: 'tlb-split' is a dependency of 'd-tlb-sets'
	from schema : http://devicetree.org/schemas/cpus.yaml#
cpus: cpu@0: 'tlb-split' is a dependency of 'i-tlb-size'
	from schema : http://devicetree.org/schemas/cpus.yaml#
cpus: cpu@0: 'tlb-split' is a dependency of 'i-tlb-sets'
	from schema : http://devicetree.org/schemas/cpus.yaml#
 2024-05-30 16:18:11 +10:00
Gwenhael Goavec-Merou d79c91daea
Merge pull request #1797 from Dasharo/s3_fix 
Change EOS S3 clock names
 2024-05-30 06:24:14 +02:00
enjoy-digital 23e654db4c
Merge pull request #1968 from VOGL-electronic/fix_liblitespi 
liblitespi: Fix #1967
 2024-05-28 15:43:07 +02:00
enjoy-digital 7a3b3dcfa2
Merge pull request #1966 from maass-hamburg/dts_zepyhr_include_cpu 
litex_json2dts_zephyr.py: include cpu
 2024-05-28 15:42:38 +02:00
enjoy-digital 914167cb75
Merge pull request #1969 from enjoy-digital/ghdl_fix 
ci: Build/Install GHDL from sources.
 2024-05-28 15:20:43 +02:00
Florent Kermarrec 5257ddaac0 ci: Build/Install GHDL from sources. 2024-05-28 14:33:05 +02:00
Matthias Breithaupt 025149c6c5 liblitespi: Fix #1967 
Make liblitespi independent from field_access_functions, since they were removed in 46911d5078

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-05-28 11:27:02 +02:00
Fin Maaß ae13f159c4 litex_json2dts_zephyr.py: include cpu 
include cpu, to share the clock-frequency with
zephyr.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-05-27 11:29:58 +02:00
Florent Kermarrec 47bab2fcff CHANGES.md: Update. 2024-05-27 08:41:58 +02:00
enjoy-digital 2235c711e6
Merge pull request #1964 from acceleratedtech/jwise/output-load-trion 
efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion
 2024-05-27 08:40:49 +02:00
enjoy-digital aa9ad61674
Merge pull request #1962 from VOGL-electronic/master 
Add support for the Efinix reconfiguration interface
 2024-05-27 08:36:40 +02:00
Joshua Wise 7ad3f2ce34 efinix: be able to specify TX_OUTPUT_LOAD on a LVDS PHY on Trion 2024-05-24 18:10:24 -04:00
Matthias Breithaupt eed89ba3a3 Add support for the Efinix reconfiguration interface 
This adds low level support for the reconfiguration interface (sometimes also called remote update by Efinix)

Signed-off-by: Matthias Breithaupt <m.breithaupt@vogl-electronic.com>
 2024-05-24 08:50:58 +00:00
enjoy-digital 56371c4d9f
Merge pull request #1961 from maass-hamburg/dts_zephyr_include_ctrl 
litex_json2dts_zephyr.py: include ctrl
 2024-05-23 15:52:24 +02:00
Fin Maaß 77683f1659 litex_json2dts_zephyr.py: include ctrl 
include ctrl, needed to implement rebooting
in zephyr.

Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
 2024-05-22 16:16:03 +02:00
Gwenhael Goavec-Merou 0af1ae8c64 soc/cores/cpu/zynqmp/core.py: added add_gpios method to connect EMIO to the PSU's GPIO controler 2024-05-22 15:55:46 +02:00
Gwenhael Goavec-Merou 44d049f3ad litex/soc/integration/soc.py: add_uart: disable check_duplicate -> required when this method is called more than once 2024-05-22 15:53:52 +02:00
Florent Kermarrec 14dbdeb0cb soc/integration/export: Disable fields_access_function by default. 2024-05-21 10:26:18 +02:00
Florent Kermarrec 05030990b2 soc/integration/export: Add LITEX_CSR_ACCESS_FUNCTIONS/LITEX_CSR_FIELDS_ACCESS_FUNCTIONS defines to allow user to disable access functions. 
-DLITEX_CSR_ACCESS_FUNCTIONS=0 to disable CSR access functions.
-DLITEX_CSR_FIELDS_ACCESS_FUNCTIONS=0 to disable CSR access functions.

User can also avoid access function generation on get_csr_header call with:
- with_access_functions=False
- with_fields_access_functions=False
 2024-05-21 10:26:13 +02:00
Florent Kermarrec 5b297f5601 soc/integration_export: Split C header generation by sections. 
- CSR Includes.
- CSR Registers/Fields Definition.
- CSR Registers Access Functions.
- CSR Registers Field Access Functions.
 2024-05-21 10:26:08 +02:00
Florent Kermarrec 4502edd33e soc/integration/export: Prepare split of C header generation in sections. 2024-05-21 10:26:04 +02:00
Gwenhael Goavec-Merou 10083f4d87
Merge pull request #1958 from nrndda/patch-1 
Simple mistake fix
 2024-05-18 21:33:25 +02:00
Dmitry 2d52c65613
Simple mistake fix 2024-05-18 19:09:13 +00:00
Florent Kermarrec 4b3f147fc8 CHANGES: Update. 2024-05-17 12:58:03 +02:00
enjoy-digital d5f9d57c2b
Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart 
Zynqmp aximaster eth i2c uart
 2024-05-17 12:54:06 +02:00
Gwenhael Goavec-Merou 943c0c263d soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP UART interface in EMIO mode 2024-05-17 11:02:41 +02:00
Gwenhael Goavec-Merou 49488e5e01 soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP i2c interface in EMIO mode 2024-05-17 11:02:31 +02:00
Gwenhael Goavec-Merou e95edaf9be soc/cores/cpu/zynqmp/core.py: added method to enable ZynqMP ethernet interface in EMIO mode (with gmii_to_rgmii) 2024-05-17 11:02:16 +02:00
Gwenhael Goavec-Merou 1986b79b9a soc/cores/cpu/zynqmp/core.py: add_axi_gp_master: removed loop over layout to have a more clear / easy to maintain connexion 2024-05-17 11:02:02 +02:00
Gwenhael Goavec-Merou c5592ca8da soc/cores/cpu/zynqmp/core.py: allows user to specify default configuration (preset) with a tcl file 2024-05-17 11:01:46 +02:00
enjoy-digital 882463d9db
Merge pull request #1955 from Dolu1990/nax64_irq 
cores/cpu/naxriscv: fix 64 bits IRQ support
 2024-05-17 08:20:46 +02:00
Dolu1990 74b300597b cpu/naxriscv: fix 64 bits IRQ support 2024-05-16 18:59:40 +02:00
enjoy-digital d7b4c7bc9c
Merge pull request #1954 from enjoy-digital/vexriscv_smp_irqs 
Add baremetal IRQ support to VexRiscv-SMP and NaxRiscv.
 2024-05-16 10:55:12 +02:00
Florent Kermarrec fbf03ec74c inteconnect/axi_lite/wishbone SRAM: Switch back to LiteXModule and add autocsr_exclude on mem to avoid AutoCSR to collect it. 
Also cleanup self.mem.get_port call.
 2024-05-16 10:36:44 +02:00
Florent Kermarrec c0d9224f09 integration/export/_generate_csr_header_includes_c: Fix refactoring issue and do not include generated/soc.h when access functions are disabled. 2024-05-16 09:19:18 +02:00
Dolu1990 d4c1a10817 cores/cpu/naxriscv: Add baremetal IRQ support 2024-05-14 14:57:29 +02:00
Florent Kermarrec e03b097e8e software/libbase/isr.c: Simplify using __riscv_plic__ define. 2024-05-14 14:47:01 +02:00
Florent Kermarrec c79e1ef95f cores/cpu/vexriscv_smp: Remove FIXME/CHECKME now that working and remove UART_POLLING flag. 2024-05-14 14:43:57 +02:00
Dolu1990 786c929f08 cores/cpu/vexriscv_smp: fix PLIC_EXT_IRQ_BASE 2024-05-14 14:24:37 +02:00
enjoy-digital 8a83585b85
Merge pull request #1953 from enjoy-digital/export_csr_c_rework 
Simplify/Cleanup C exports and disable Fields accessors generation by default.
 2024-05-14 12:54:48 +02:00
Florent Kermarrec 8eaa53ae9a test/test_cpu: Disable cv32e40p test (need to update/wait for pythondata to be updated). 2024-05-14 12:53:09 +02:00