a36a208dd1
sim: use (mandatory) ncycles when starting a simulation with no active functions
2014-04-13 15:16:27 +02:00
fef08e8c70
mibuild: add bitstream_ext parameter to platforms
2014-04-11 23:28:39 +02:00
82e4980f5c
mibuild/altera_quartus: set top_level_entity
2014-04-11 23:27:04 +02:00
600ce55f91
mibuild/altera_quartus: add support for verilog include
2014-04-11 23:24:51 +02:00
4240058979
README: rewrap
2014-04-08 17:22:44 +02:00
2f6f584adb
update README
2014-04-08 17:11:27 +02:00
f76da70cda
software/libcompiler-rt: adapt to new upstream directory organization
2014-04-08 15:29:23 +02:00
0c3f8f703d
targets/simple: add dummy SDRAM + flash boot address
2014-04-08 15:25:49 +02:00
ce378f47d3
test/SyncFIFOCase: better test bench termination
2014-04-07 00:05:08 +02:00
e94f30f15d
mibuild/xilinx_ise: move overwrite option to default options
2014-04-05 12:15:15 +02:00
9ff6cc8403
mibuild/xilinx: make par and map options configurable
2014-04-05 12:15:14 +02:00
ac1363565d
genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered
2014-04-05 12:15:14 +02:00
9deddbdfbc
test/test_cordic: fix for new Simulation API
2014-03-24 15:01:44 -07:00
7649028bdc
test/support: fix default ncycles
2014-03-24 15:01:44 -07:00
0023b742e4
genlib/coding: gracefully handle flen(i) < 2
2014-03-19 18:12:27 -07:00
0836f2814a
bus/csr: new simulation api
2014-03-19 18:12:27 -07:00
b03d9f4c14
genlib/fifo: add flush, expose level in SyncFIFO
...
AsyncFIFO would need versions of flush and level in each clock domain
plus some handshaking on double flush.
Signed-off-by: Robert Jordens <jordens@gmail.com>
2014-03-15 23:10:46 -07:00
3882a07ae5
Add Python flasher
2014-02-28 09:40:49 -08:00
9e784fc82c
Generate mem.h from SoC description
2014-02-21 17:55:05 +01:00
bf6ab2b4f6
mibuild/generic_platform: fix default value for connectors
2014-02-17 17:40:15 +01:00
c98b9ecbcb
mibuild/platforms/papilio_pro: add expansion connectors
2014-02-16 23:54:11 +01:00
cb2c9f9f7a
mibuild: support for expansion connectors
2014-02-16 23:53:50 +01:00
fce46ac0ca
Simplify use of external targets/platforms/cores + add default platform in targets
2014-02-16 14:51:52 +01:00
f7fa9cf11e
make.py: support setting flash proxy directory
2014-02-15 14:13:25 +01:00
a23dffd2c2
bios: update banner
2014-02-15 14:02:09 +01:00
f55943ae18
new action syntax for make.py + support xc3sprog
2014-02-15 14:01:50 +01:00
e4273be517
targets/simple: use XIP from SPI flash
2014-02-14 15:48:15 +01:00
bdb47e7977
dvisampler: replace parity with sof
2014-02-13 22:45:27 +01:00
88d4962a1c
targets/mlabs_video: use outer video inputs
2014-02-13 22:07:23 +01:00
42c25f44ad
videostream: add downscaler core + test
2014-02-10 00:12:57 +01:00
2a3803d3a1
videostream: add single chopper
2014-02-09 00:53:30 +01:00
b6a00e86e4
videostream: add compacter and packer
2014-02-08 18:39:01 +01:00
d26330a9b9
Update doc with new simulation API
2014-02-07 23:08:59 +01:00
25acf17312
Refresh testbenches and convert to new API
2014-01-28 13:50:01 +01:00
2ab939e69d
fix SimActor TB terminations
2014-01-28 00:03:56 +01:00
90f0dfad63
Add 'passive' simulation functions that are not taken into account while determining when to stop the simulator
2014-01-27 23:58:46 +01:00
63c1d7e4b7
New simulation API
2014-01-26 22:19:43 +01:00
e464935119
downscaler: add chopper module
2014-01-21 15:56:51 +01:00
8f69d9b669
bank/eventmanager: add SharedIRQ
2014-01-06 22:13:06 +01:00
ad974a07ef
gensoc: support for user-defined UART and add default values for SRAM and L2 sizes
2014-01-06 22:12:42 +01:00
be1c8551d2
migen/fhdl/tools: speed up group_by_targets (halves the mixxeo runtime)
2013-12-17 18:40:49 +01:00
4e9dc297fd
platforms/rhino: add GPMC wait pin
2013-12-14 14:32:34 +01:00
a20688f777
fhdl/simplify/FullMemoryWE: fix WE slice for multi-port mems
2013-12-13 00:02:50 +01:00
3196462311
add support for Verilog include paths
2013-12-12 23:17:51 +01:00
c95b9d6d76
gensoc: use add_verilog_include_path
2013-12-12 23:17:16 +01:00
ba46cd3da1
make.py: update description
2013-12-12 23:16:59 +01:00
860f27300f
make: add decorator option
2013-12-12 17:37:46 +01:00
adda930c68
fhdl/simplify: add FullMemoryWE decorator that splits memories to remove partial WEs
2013-12-12 17:37:31 +01:00
adffec35f6
utils/misc: add gcd_multiple function to compute GCD or any number of integers
2013-12-12 17:36:50 +01:00
c13fe1bc63
specials/Memory: allow for more flexibility in memory port signals
2013-12-12 17:36:17 +01:00
Sebastien Bourdeauducq
Florent Kermarrec
Robert Jordens
Sebastien Bourdeauducq