46c1c5c16f
targets/kcu105: remove main_ram_size_limit
2020-01-17 12:27:21 +01:00
5913c91caa
SoCSDRAM: rename main_ram_size_limit to max_sdram_size and make it a parameter of SoCSDRAM, expose SoCSDRAM parameters to user
2020-01-17 12:16:08 +01:00
1c465f89b6
build/lattice: add add_false_path_constraint method for API compatibility but false paths are not yet used/translated to .lpf file
2020-01-17 10:17:19 +01:00
b4ba2a47ef
soc/cores/uart: set rx_fifo_rx_we to True on UARTCrossover
2020-01-17 06:32:00 +01:00
d15c911cac
BlackParrot initial commit
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w/ Litex BIOS simulation including LiteDRAM
w/ Litex BIOS working on FPGA excluding LiteDRAM
2020-01-16 19:13:02 -05:00
5aa516cb8d
soc/cores/uart: add rx_fifo_rx_we parameter to pulse rx_fifo.source.ready on rxtx register read.
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When UARTCrossover is used over Etherbone, acking data directly with the read avoid the write/read round-trip
and speed up communication a lot (>10x).
2020-01-16 19:45:41 +01:00
862e784eae
cpu/vexriscv: use 32-bit signal for externalResetVector
2020-01-16 16:20:25 +01:00
f2a1673f46
targets/arty/genesys2: fix EthernetSoC/EtherboneSoC selection
2020-01-16 13:17:33 +01:00
990870d061
targets/genesys2: add EtherboneSoC
2020-01-16 12:32:59 +01:00
820e79bf9c
platforms/de0nano: specify gpio for serial
2020-01-16 12:32:25 +01:00
ba366d42d0
targets: cleanup EthernetSoC
2020-01-16 10:14:42 +01:00
a26853702c
soc/interconnect/packet/Depacketizer: use both sink.valid and sink.ready to update sink_d, fix Etherbone regression on Arty.
2020-01-16 09:46:54 +01:00
a168ecbabd
targets/arty: add EtherboneSoC
2020-01-16 09:11:44 +01:00
7a4ecfa59d
targets/kcu105: update
2020-01-15 13:17:59 +01:00
68e225fb45
test/test_targets: update
2020-01-15 13:09:03 +01:00
42efa99826
SoCCore: set default integrated_rom/ram_size to 0. For targets, defaults values are provided by soc_core_args.
2020-01-15 10:59:01 +01:00
4050e60834
SoCCore: use hex for integrated_rom/sram_size
2020-01-13 20:01:45 +01:00
f818755c9c
Merge pull request #339 from gsomlo/gls-csr-cleanup
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CSR Improvements and Cleanup
2020-01-13 19:57:59 +01:00
f1606dbc72
tools/litex_sim: use default integrated_rom_size
2020-01-13 17:39:23 +01:00
4648db0c2a
cores/uart/UARTInterface: remove connect method
2020-01-13 16:58:00 +01:00
6c9f418d26
soc_core: fix uart stub
2020-01-13 16:56:31 +01:00
b073ebadf6
bios/sdram: switch to updated CSR accessors, and misc. cleanup
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Revert to treating SDRAM_DFII_PIX_[RD|WR]DATA CSRs as arrays
of bytes, but use the new uintX_t array accessors for improved
legibility, and to avoid unnecessary byteswapping.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
2c39304110
software, integration/export: rename and reimplement CSR accessors
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Implement CSR accessors for all standard integer types and
combinations of subregister alignments (32 or 64 bit) and
sizes (i.e., csr_data_width 8, 16, or 32).
Rename accessors to better reflect the size of the register
being accessed, and correspondingly update the generation
of "csr.h" in "export.py".
Additionally, provide read/write accessors that superimpose arrays
of standard unsigned C types over a CSR register (which may itself
be spread across multiple subregisters).
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-01-13 10:09:02 -05:00
63cd23c9c3
cpu/vexriscv: revert mem_map_linux/main_ram
2020-01-13 16:02:32 +01:00
83a7225ccc
SoCCore: set integrated rom/sram size default values in soc_core_args and use it in targets
2020-01-13 15:03:36 +01:00
6e3f25a7e0
cpu/vexriscv/mem_map_linux: update main_ram to 0x40000000
2020-01-13 14:40:26 +01:00
fe14b9cf86
targets/genesys2: update self.register_sdram
2020-01-13 14:39:45 +01:00
39ce39a298
soc_sdram: add l2_data_width parameter to set minimal l2_data_width to improve DRAM accesses efficiency.
2020-01-13 13:00:17 +01:00
23175190d8
cores/uart: add UARTCrossover
2020-01-13 10:14:38 +01:00
2f03d3234e
cores/uart/UART: add stream interface (phy=None), add connect method and use this for UART Stub/Crossover.
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A bridged/crossover UART can now just be created by:
- passing uart_name="stream" to SoCCore/SoCSDRAM.
- adding a crossover UART core to the design:
# UART Crossover (over Wishbone Bridge
from litex.soc.cores.uart import UART
self.submodules.uart_xover = UART(tx_fifo_depth=2, rx_fifo_depth=2)
self.add_csr("uart_xover")
self.comb += self.uart.connect(self.uart_xover)
2020-01-13 09:20:40 +01:00
d92bd8ffaa
gen/fhdl/verilog: fix signed init values
2020-01-12 22:06:35 +01:00
ff066a5e09
Merge pull request #338 from DurandA/master
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Add optional 'ignore-loops' flag to nextpnr
2020-01-12 21:18:23 +01:00
26fe45fce1
cores/uart: rename BridgedUART to UARTEmulator and rework/simplify it. Also integrated it in SoCCore with uart_name="emulator"
2020-01-12 21:13:02 +01:00
d40bf9d8a7
Merge pull request #340 from xobs/bridged-uart
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uart: add BridgedUart
2020-01-12 20:40:27 +01:00
5079a3c32e
uart: add BridgedUart
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This version of the UART adds a second, compatible UART after
the first. This maintians software compatibility, and allows a
program running on the other side of the litex bridge to act as
a terminal emulator by manually reading and writing the second
UART.
Signed-off-by: Sean Cross <sean@xobs.io>
2020-01-12 19:52:42 +10:00
d24a4b5428
Add optional 'ignore-loops' flag to nextpnr
2020-01-10 16:07:56 +01:00
f70dd48279
bios/sdram: add memspeed
2020-01-10 14:25:46 +01:00
fa22d6aa82
wishbone/Cache: avoid REFILL_WRTAG state to improve speed.
2020-01-10 14:25:07 +01:00
f408527dd4
soc/cores/cpu: add riscv64-linux toolchain support for risc-v cpus.
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Toolchain can be downloaded from https://toolchains.bootlin.com/
2020-01-10 08:49:34 +01:00
8889821c54
targets: sync with litex-boards
2020-01-09 21:12:00 +01:00
aba8fc5c94
build/altera/quartus: allow multiple call of add_period_constraint if constraint is similar.
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Similar to the changes already applied to Xilinx backend.
2020-01-09 19:45:51 +01:00
e318287ec2
Merge pull request #337 from gregdavill/spi-flash
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soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
2020-01-09 13:24:17 +01:00
49781467d7
soc/cores/spi_flash: Don't tristate DQ2/DQ3 when bitbanging
2020-01-09 21:53:00 +10:30
2cf95e9f93
platforms/minispartan6: rename sd to sdcard and regroup data lines
2020-01-09 11:12:37 +01:00
e99740e814
platforms/nexys4ddr: add sdcard pins
2020-01-09 11:00:54 +01:00
83ad674feb
build/lattice/trellis: use a single fonction to parse device
2020-01-08 19:38:27 +01:00
018c7ca890
Merge pull request #336 from kbeckmann/trellis-speed
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trellis: Pass speed argument to nextpnr
2020-01-08 19:17:04 +01:00
426ab676e8
trellis: Pass speed grade argument to nextpnr
2020-01-08 08:42:29 +01:00
fd4cbd8053
Merge pull request #331 from betrusted-io/xadc_mods
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WIP: add support for DRP on XADC
2020-01-06 18:09:12 +01:00
378722a7ef
soc/cores/xadc: define analog_layout and simplify analog_pads connections
2020-01-06 16:28:48 +01:00
Florent Kermarrec
sadullah
Gabriel Somlo
Sean Cross
Arnaud Durand
Greg Davill
Konrad Beckmann