71993edae4
Add init file in sdram/phy dir
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Without __init__.py file, when using setup.py, setuptools' find_package() function does not find the files in sdram/phy package. Hence .egg file entirely misses sdram/phy directory
More info here: https://bitbucket.org/pypa/setuptools/issues/97
2015-09-21 23:46:16 +08:00
a1e4183b3f
sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY
2015-08-22 12:50:41 +02:00
de87d65f68
sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis, Novena) modules.
2015-08-22 12:42:44 +02:00
50e857e99c
sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.
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Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock.
Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).
2015-08-22 12:17:48 +02:00
158fbe49ac
sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that)
2015-08-22 11:47:26 +02:00
4acab79987
sdram/module: cleanup indent
2015-08-20 22:15:06 +02:00
c03ef526eb
sdram/phy/s6ddrphy: add DDR3 support
2015-08-04 12:29:42 +02:00
52fba05e26
sdram/phy/initsequence: add burst chop 4 (BC4) for DDR3
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This is needed for half rate controllers with burst length of 4.
For best efficiency quarter rate controllers should be used.
2015-08-04 11:19:20 +02:00
e6da1d16b2
wishbone2lasmi: fix "READ_DATA" state
2015-07-09 10:40:32 +02:00
3b9f287bab
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
2015-06-17 15:30:30 +02:00
1bb2580779
sdram: use new Migen Converter in Minicon frontend and small cleanup
2015-06-02 19:37:08 +02:00
f96a856c97
sdram/phy: fix simphy memory usage
2015-06-02 19:33:09 +02:00
f40140dba5
sdram: refactor minicon and fix issues with DDRx memories
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- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
2ccb5655c9
global: more pep8
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we will have to continue the work... volunteers are welcome :)
2015-04-13 18:02:26 +02:00
fc68d915c1
global: pep8 (E261, E271)
2015-04-13 17:16:12 +02:00
f3c010c1d5
global: pep8 (E225)
2015-04-13 17:01:05 +02:00
796119fcaf
global: pep8 (E203)
2015-04-13 16:53:07 +02:00
ca7019fa0d
global: pep8 (E231)
2015-04-13 16:51:00 +02:00
9ad90b531e
global: pep8 (E201)
2015-04-13 16:48:51 +02:00
f68423f423
global: pep8 (E302)
2015-04-13 16:47:22 +02:00
d9e09707ae
global: pep8 (replace tabs with spaces)
2015-04-13 16:19:55 +02:00
d6c19858fa
s6ddrphy: redo phase_sel, get rid of CLOCK_DEDICATED_ROUTE
2015-04-10 16:12:29 +08:00
382ed013af
minor cleanups
2015-04-02 14:40:29 +08:00
b313772a0c
sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
2015-03-29 12:34:40 +02:00
a8d91c0c1d
sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
2015-03-28 16:35:15 +01:00
75ee8a5db9
sdram/phy/simphy: OK with DDR3
2015-03-28 01:59:55 +01:00
51ce7cad6f
sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
2015-03-28 01:18:35 +01:00
a95b3f8f13
sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
2015-03-28 01:17:50 +01:00
7fe748e1b0
sdram/module: clean up tREFI. (use 64ms/8k or 4k)
2015-03-28 01:09:21 +01:00
9137b91e9e
sdram: remove nbits from modules and databits from GeomSettings
2015-03-26 23:27:37 +01:00
9a9af17aca
sdram/phy/simphy: remove use of iter
2015-03-26 23:02:23 +01:00
e6de4b1bf9
sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
2015-03-26 22:28:32 +01:00
257706517e
software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
2015-03-26 00:01:42 +01:00
ff11cb97a9
sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
2015-03-25 17:22:26 +01:00
ba8b24df57
sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
2015-03-25 16:57:38 +01:00
7ea9e2ba89
sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
2015-03-25 16:56:29 +01:00
92f81409f2
sdram/module: fix tREFI on AS4C16M16
2015-03-22 03:20:02 +01:00
30c2521eb0
sdram: pass sdram_controller_settings to SDRAMSoC
2015-03-21 23:12:18 +01:00
70469e1f37
sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
2015-03-21 21:32:39 +01:00
c60d99583d
sdram/module: add tREFI uniformization to TODO
2015-03-21 18:59:16 +01:00
0f9b0c6f0f
sdram/module: add MT47H128M8 DDR2 (used for a customer)
2015-03-21 18:52:10 +01:00
45eb5090db
sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
2015-03-21 18:41:59 +01:00
a560ba35bd
sdram/module: add AS4C16M16 for minispartan6
2015-03-21 18:38:53 +01:00
854058a8db
sdram/module: add description and TODO list
2015-03-21 17:44:04 +01:00
52924ee1f2
sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
2015-03-21 17:25:36 +01:00
fd2f8d4bb4
sdram: define MT46V32M16 and use it on m1/mixxeo
2015-03-21 17:04:58 +01:00
de2f1c31d5
sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
2015-03-21 16:56:53 +01:00
6e4b7c6cfd
sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
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req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
2015-03-21 12:55:39 +01:00
905be50451
sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
2015-03-03 09:55:25 +01:00
9210272356
sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
2015-03-03 09:23:21 +01:00
Rohit Kumar Singh
Florent Kermarrec
Robert Jordens
Sebastien Bourdeauducq