944732aa19
soc/add_sdram: Also remove ResetInserter on axi.AXI2Wishbone.
2021-09-27 15:46:19 +02:00
ce0551b44a
cpu/rocket/core: Remove ResetInserter on adapters.
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Previously, the SoCController was only reseting the CPU, which required adding
these ResetInserters. Now that the SoCController resets both CPU and peripherals
these ResetInserters are redundant and no longer useful.
2021-09-27 09:05:46 +02:00
c43132f81f
Merge pull request #1040 from gsomlo/gls-rocket-smp
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Rocket SMP support
2021-09-23 10:56:06 +02:00
07e47d9357
cpu/rocket: add quad-core (smp) variants
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- 4-core "full" (fpu-enabled) variants with double, quad mem. bus width
- 4-core "linux" (fpu-less) variant with single (64-bit) mem. bus width
2021-09-22 16:59:04 -04:00
901b19828c
cpu/rocket: include core count as per-variant parameter
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Repurpose (and rename to `CPU_SIZE_PARAMS`) the current
`AXI_DATA_WIDTHS` array. In addition to axi widths for
mem and mmio ports, also include each variant's number
of cores, to facilitate dynamically generated per-core
signals.
2021-09-22 16:58:11 -04:00
e6aaa40d2d
cpu/rocket: bios support for SMP
2021-09-22 13:51:18 -04:00
2bc8124114
cpu/rocket: crt0, boot-helper: use temp. registers (cosmetic)
2021-09-22 13:51:18 -04:00
1d302c56da
Merge pull request #1041 from gsomlo/gls-vex-smp-fix
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cpu/vexriscv_smp/crt0.S: only boot core should run data_init
2021-09-22 19:35:47 +02:00
60c6077c32
remote/comm_udp: Add padding bytes to Etherbone probe.
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Now required with LiteEth dropping exceeding payload.
2021-09-22 16:52:08 +02:00
23b2ac2013
cpu/vexriscv_smp/crt0.S: only boot core should run data_init
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Also, no need for non-boot cores to `call smp_slave`, it's the
immediately following instruction for them already.
2021-09-22 09:55:20 -04:00
027f7aa645
tools/litex_json2dts_linux: Fix typo.
2021-09-21 14:32:20 +02:00
84f1afd6d4
tools/litex_json2dts_linux: Remove mem=/, init= and swiotlb= bootargs.
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Were not useful as pointed by @shenki and @stffrdhrn.
2021-09-21 13:37:25 +02:00
b1b1e92ad0
Merge pull request #1032 from stffrdhrn/json2dts-sdcard
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Json2dts sdcard booting
2021-09-21 13:13:07 +02:00
9f75c73d6b
build/xilinx/common: Fix Ultrascale SDROutput/Input.
2021-09-21 10:30:36 +02:00
233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok
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Remove rsp_payload_response_ok from Vex/CFU hookup code.
2021-09-21 09:43:15 +02:00
08779202f4
build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap).
2021-09-21 08:18:06 +02:00
1be449d72b
Remove rsp_payload_response_ok from Vex/CFU hookup code.
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The port has already been removed from VexRiscv (issue #1036 ).
Signed-off-by: Tim Callahan <tcal@google.com>
2021-09-20 15:02:51 -07:00
1e24fd87d1
cores/gpio: Simplify #1035 .
2021-09-20 17:34:46 +02:00
6251474b39
Merge pull request #1035 from lschuermann/dev/litex-sim-gpio
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litex_sim: optionally add GPIOTristate core
2021-09-20 17:21:29 +02:00
0daa86a8bb
Merge pull request #1038 from antmicro/crosslinknx-ddr-tristate
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build/lattice: add DDRTristate for Crosslink-NX
2021-09-20 14:14:40 +02:00
49d8000d49
gowin/common: Add Differential Input/Output support.
2021-09-20 14:14:06 +02:00
9c373242af
gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern.
2021-09-20 11:47:32 +02:00
6c0a758468
Added syn_useioff attribute support for Oxide toolchain and for the DDRTristate in Crosslink NX
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-20 11:02:01 +02:00
5519d908e8
cores/video: Rename VideoECP5HDMIPHY to VideoHDMIPHY since in fact generic and can be used on other FPGAs (ex Tang Nano 4k).
2021-09-20 09:29:05 +02:00
4fe085cc1c
cores/clock: Add initial GW1NSR's PLL support.
2021-09-20 08:39:25 +02:00
76c782c546
inetgration/builder: Check for full software re-build only when a CPU is used.
2021-09-20 08:31:22 +02:00
46cd9c5a5c
tools: Minor #1030 cleanups.
2021-09-17 14:37:48 +02:00
8ccb1a91c9
build/openfpgaloader/flash: Add external parameter to allow flashing external SPI Flash when available.
2021-09-17 14:37:14 +02:00
24f0432253
Merge pull request #1030 from teknoman117/fix-lxserver-pcie-crossover
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Fixes to allow crossover uart over PCIe with lxterm and litex_server
2021-09-17 14:28:25 +02:00
a7c9e4ed42
Merge pull request #1033 from caverar/patch-1
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Linker fix for initialized global variables
2021-09-17 14:23:44 +02:00
7f8e2e39f3
cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes.
2021-09-16 18:56:05 +02:00
e8e14d8ca5
build/lattice: add DDRTristate for Crosslink-NX
2021-09-16 14:23:02 +02:00
beb7cc691d
CHANGES: Do 2021.08 release.
2021-09-15 15:05:47 +02:00
343d88e837
setup.py: Expose litex_contributors tool.
2021-09-15 14:38:45 +02:00
05b960d09b
CHANGES: Update.
2021-09-15 12:08:30 +02:00
02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll
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Fix premature selection of full PLL config with no feedback
2021-09-15 08:52:59 +02:00
91ec6e0da8
clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond
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Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs. Emit the same attributes that Diamond's PLL tool does.
2021-09-15 00:07:43 -05:00
6733a3e3e6
clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search
2021-09-15 00:07:43 -05:00
88d302d4db
soc/alloc_region: Ensure allocated Region is aligned on size.
2021-09-14 18:08:07 +02:00
694878a35a
integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints.
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Some boards require specific constraints, so disable them in this case and put constraints in the target file.
2021-09-13 19:32:50 +02:00
8670ac4902
litex_sim: add optional GPIOTristate core
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Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 12:33:41 +02:00
cb7b0f44cf
tools/litex_sim: Fix mem_map.
2021-09-13 11:33:16 +02:00
af8459301c
litex/soc/cores/gpio: support external tristate buffer
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Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 11:17:54 +02:00
a235eaf0cd
Linker fix for initialized global variables
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I found that in some cases, initialized global variables don't work with user libraries, so a little change to the linker that I use, taken from the demo file, seems to solve the problem . I think that make more sense to put the global variables in sram and initial values in the main_ram, similar to the bios linker.
2021-09-13 00:44:30 -05:00
ea06948c62
json2dts_linux: Add configuration for root device
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This allows setting a root device other than ram0, this is useful
when using a rootfs from the SD card. Doing this makes boot time
faster and saves on memory footprint used by an in ram initrd.
2021-09-12 14:44:22 +09:00
ec2f2a6af5
json2dts_linux: Use liteuart earlycon
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Now that liteuart earlycon is upstream we can use it. This means
all litex soc's should be able to get an earlycon now. Tested on
mor1kx.
2021-09-12 14:42:52 +09:00
378d129c5f
json2dts_linux: Allow disabling of initrd
2021-09-12 14:42:46 +09:00
9ec45181dd
.gitignore: ignore visual studio code settings
2021-09-08 18:06:45 -07:00
ab3d7e86f2
litex/tools: add command line options and fixes for lxterm to allow crossover uart over PCIe
2021-09-08 18:06:12 -07:00
e0e9311ceb
interconnect/wishbone: Specify Wishbone version ( #999 ).
2021-09-08 17:33:01 +02:00
Florent Kermarrec
Gabriel Somlo
Andwer E Wilson
Tim Callahan
Maciej Kurc
Pawel Sagan
George Hilliard
Leon Schuermann
Camilo Andres Vera Ruiz
Stafford Horne
Nathaniel R. Lewis