Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
7000 commits 42 branches 14 tags 31 MiB
Commit graph

7000 commits

This branch
This branch
All branches
Author SHA1 Message Date
Florent Kermarrec
9ab82cacda soc/add_ethernet/etherbone: Fix conflicts/Update. 2021-09-27 17:43:39 +02:00
Leon Schuermann
339fabf615 litex/soc: support model-version of GMII PHY in add_ether{net,bone} 
This not only tests for the precise PHY model, but also whether there
is a model attribute in the ethphy instance and whether that is set to
True.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-01 20:44:55 +02:00
Leon Schuermann
2852e80eae tools/litex_sim: split out construction of ethphy 
The different branches each constructed their own ethphy. We can split
this out, which increases code reuse and allows to use the GMII and
XGMII interface types with all of Ethernet, Etherbone or
Ethernet+Etherbone.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-01 20:44:55 +02:00
Leon Schuermann
08a14e8cf1 litex_sim: add GMII verilator module and add support in litex_sim 
Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-01 20:44:50 +02:00
Leon Schuermann
7b533a032d litex_sim: rewrite XGMII verilator module and add support in litex_sim 
Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-01 20:44:45 +02:00
Leon Schuermann
92ceb8f73d litex_sim: rename clk_edge to clk_edge_state, add clk_edge enum 
This renames the `clk_edge_t` struct to `clk_edge_state_t`, given it
only tracks the previous clock edge state.

Furthermore introduce a new `enum clk_edge` (typedef'd to
`clk_edge_t`) which represents all possible clock edges and add a
function (`clk_edge`) to retrieve the type of current clock edge as a
`clk_edge_t`.

Signed-off-by: Leon Schuermann <leon@is.currently.online>
 2021-09-01 20:44:41 +02:00
Florent Kermarrec
ce5864983d soc/add_cpu: Add memory mapping overrides to build log and make an exception for the CPUNone case. 
A regular CPU can provides specific mapping constraints and we are overriding provided mapping
with these constraints.

The case of CPUNone is different and we can do the opposite: Give priority to User's mapping.

For the regular CPU case, the override was done silently, it is now logged during the build.
 2021-07-30 15:00:10 +02:00
Florent Kermarrec
c80d5723c9 soc/add_spi_flash: Reduce default_divisor. 2021-07-30 12:32:57 +02:00
Florent Kermarrec
6100620634 bios/main: Display Flash in SoC capabilities. 2021-07-29 19:26:01 +02:00
Florent Kermarrec
518a3e1f65 liblitespi/spiflash: Use software defined constants and fix spiflash_master_write (mmap renamed to core). 2021-07-29 19:25:28 +02:00
Florent Kermarrec
ab48461d6a soc/add_spi_flash: Generate useful software constants from SPIFlash module. 2021-07-29 19:24:30 +02:00
Florent Kermarrec
f0a258e0a7 soc/add_spi_flash: Use cached SoCRegion, fixes #981. 2021-07-29 18:53:04 +02:00
Florent Kermarrec
bb9701b5f6 soc/add_spi_flash: Move integration code for previous LiteX SPI Flash core to compat/soc_add_spi_flash.py. 2021-07-29 18:48:03 +02:00
Florent Kermarrec
60c4a1b667 liblitespi/spiflash: Review #979 and other cleanups. 
- Rename optional #define and allow defining them externally.
- Add comments.
- Rename FLASH_CHIP_MX25L12833F_QUAD to SPIFLASH_MODULE_QUAD_CAPABLE.
- Rename FLASH_CHIP_MX25L12833F_QPI  to SPIFLASH_MODULE_QPI_CAPABLE.

The instructions used for QUAD/QPI are probably different between chips, we could
imagine providing them through the LiteX integration based on the passed SPI Flash
module.
 2021-07-29 18:21:07 +02:00
enjoy-digital
1933beadb1
Merge pull request #979 from antmicro/litespi-qpi 
WIP: enable QPI mode in liblitespi
 2021-07-29 17:59:51 +02:00
Florent Kermarrec
c5b5abd103 soc/add_spi_flash: Rename spiflash_mmap to spi_flash_core (since LiteSPI inclule MMAP and Master Interface). 2021-07-29 17:42:07 +02:00
Florent Kermarrec
505c8b85d6 soc/add_spi_flash: Reduce LiteSPIPHY default divisor to max(2, self.sys_clk_freq/clk_freq). 
One small FPGAs running the BIOS from SPI Flash, the default divisor of 9 was slowing down too
much BIOS boot time (It was OK on reboot after liblitespi auto-calibration). Reduce the default
divisor to avoid this.
 2021-07-29 17:16:47 +02:00
Florent Kermarrec
14d60661b9 software/bios/main: Generate Initialization banner for SPIFlash. 2021-07-28 10:55:02 +02:00
Florent Kermarrec
8415e5d6ac integration/soc/add_spi_flash: Add LiteSPI initial support (enabled when module is provided). 
Test on iCEBreaker in 1X/4X mode for now. In the future, we could probably deprecate support
for old SPIFlash core.
 2021-07-27 19:21:54 +02:00
Florent Kermarrec
80e9d2cea9 soc/interconnect/stream: Support n=1 case on Multiplexer/Demultiplexer. 
Required by LiteSPI when only one Core is connected to the PHY (ex when disabling Master or MMAP).
 2021-07-27 16:57:22 +02:00
enjoy-digital
94c934d2fb
Merge pull request #980 from developandplay/update-blackparrot-imafd 
Update blackparrot imafd
 2021-07-27 08:33:32 +02:00
developandplay
c36e2ae4e8 Add imafd support 2021-07-27 00:44:32 +02:00
developandplay
6ba514ee96 Separate BlackParrot code from adapter code 2021-07-27 00:43:09 +02:00
enjoy-digital
3387853b6b
Merge pull request #977 from antmicro/jboc/gtkw-endpoint 
GTKWSave: improved support for Endpoint
 2021-07-26 15:01:49 +02:00
Filip Kokosinski
0a0e337754 soc: software: liblitespi: enter QPI mode when using MX25L12833F 2021-07-26 14:32:56 +02:00
Florent Kermarrec
1ce48a973b clock/lattice_ecp5: Fix and rework 4-output solver implementation. 
The implementation was causing regressions on actual designs, rework done:
- Only keep a common iteration loop as before.
- Add iteration on CLKO dividers (to fall in the VCO range).
- Do the iterations as before, if while doing it we find a clock suitable for feedback: just use it.
- If no feedback clock has been found: create it (if at least one free output available, if not raise an error).
 2021-07-26 14:00:00 +02:00
Jędrzej Boczar
4636a841d3 build/sim/gtkwave: automate handling of Endpoint and other stream primitives 2021-07-22 15:49:20 +02:00
enjoy-digital
751e99690e
Merge pull request #965 from thirtythreeforty/ecp5-pll-x4 
ECP5PLL: implement 4-output solver
 2021-07-21 19:08:18 +02:00
enjoy-digital
a782596513
Merge pull request #975 from cklarhorst/master 
soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode
 2021-07-21 11:57:21 +02:00
Christian Klarhorst
e17a010866 soc/add_sdcard: Fix IRQ code, only add IRQs depending on mode 2021-07-20 22:08:36 +02:00
Florent Kermarrec
c64c6e4056 cpu/blackparrot: Re-map csr and keep the lower 128MBs for the SoC IO auto-allocation. 2021-07-20 12:05:54 +02:00
enjoy-digital
1bf7abfc8a
Merge pull request #970 from trabucayre/openfpgaloader_check_type 
openfpgaloader: improves freq conversion type
 2021-07-19 09:58:21 +02:00
Gwenhael Goavec-Merou
e3f577e0be openfpgaloader: improves freq conversion type 2021-07-17 17:02:22 +02:00
Florent Kermarrec
e0d5a7bff5 interconnect/packet/Packetizer/Depacketizer: Avoid generating unaligned logic when aligned. 2021-07-15 19:00:50 +02:00
Florent Kermarrec
0a919e709f interconnect/packet: Improve PacketFIFO to handle payload/param separately. 
Useful to save resources and store Stream's params more efficiently.
 2021-07-15 18:06:03 +02:00
Florent Kermarrec
b2f8fa5464 gen/fhdl/verilog: Make DummyAttrTranslate a dict. 2021-07-15 16:48:24 +02:00
enjoy-digital
bf52c1083f
Merge pull request #969 from trabucayre/openfpgaloader_add_cable_and_freq_options 
openfpgaloader: add cable and freq options
 2021-07-15 12:18:01 +02:00
Florent Kermarrec
730b57d9cd build/gowin: Add initial timing constraints support. 2021-07-15 11:06:03 +02:00
Florent Kermarrec
10ea45da55 build/microsemi/common: Cleanup MicrosemiPolarfireAsyncResetSynchronizerImpl. 2021-07-15 10:01:52 +02:00
Florent Kermarrec
2b393254da build: Simplify attr_translate (Now automatically defaults to None when not explicitely listed). 
Most of the attributes are Xilinx specific, it does not make sense to provide them on other FPGA devices.
 2021-07-15 09:59:15 +02:00
Florent Kermarrec
bdc32171fd gen/fhdl/verilog/_printattr: Avoid trying translating attribute when not supported by Toolchain. 2021-07-15 09:57:15 +02:00
Florent Kermarrec
4fd974be10 build/gowin: Minor cleanups. 2021-07-15 09:36:41 +02:00
Gwenhael Goavec-Merou
3706ed7416 openfpgaloader.py: cast int to str 2021-07-14 17:50:50 +02:00
Gwenhael Goavec-Merou
c984a4dbc8 openfpgaloader: add cable and freq options 2021-07-14 16:48:29 +02:00
Florent Kermarrec
756503ab92 clock/gowin_gw1n: Add Initial On-Chip Oscillator support. 
Ex: self.submodules.osc = GW1NOSC(device="GW1N9K", freq=10e6)
 2021-07-14 11:42:35 +02:00
Florent Kermarrec
6fc87f7c85 build/gowin/common: Add DDRInput/DDROutput implementations. 2021-07-14 10:01:54 +02:00
Florent Kermarrec
a8cea15b95 cores/clock/gowin_gw1n/create_clkout: Add reset support (through AsyncResetSynchronizer) and enable it by default. 
Should be based on PLL's lock but does not seem stable, so use reset input for now.
 2021-07-14 09:38:23 +02:00
Florent Kermarrec
cfbc06c297 build/gowin/common: Add AsyncResetSynchronizer implementation. 2021-07-14 09:37:00 +02:00
enjoy-digital
fab6512928
Merge pull request #967 from JosephBushagour/jbushagour_assembly_interoperability 
Make "generated/soc.h" able to be included in assembly files.
 2021-07-13 10:47:59 +02:00
enjoy-digital
df67b65a0a
Merge pull request #957 from pftbest/fix_fst 
Fix compile error when FST traces are enabled on macOS.
 2021-07-13 10:38:40 +02:00