enjoy-digital
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0bd2abf68d
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Merge pull request #1250 from pftbest/connect_to_pads_last
Fix missing "last" pin connection when using connect_to_pads
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2022-03-24 14:46:25 +01:00 |
Florent Kermarrec
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967ea12364
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cpu/vexriscv_smp: Fix pbus data-width (Max of icache/dcache-width).
Fix boot with > 1 CPU or with FPU when using --with-wishbone-memory.
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2022-03-24 14:34:38 +01:00 |
Florent Kermarrec
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0ac3d677b5
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bios/main: Test Main RAM only when not pre-initialized (corrupt contents otherwise).
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2022-03-24 14:34:29 +01:00 |
Florent Kermarrec
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d3f3f658cb
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integration/soc: Generate RAM_INIT config defined when ram is initialized.
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2022-03-24 14:34:26 +01:00 |
Vadzim Dambrouski
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c1898b9355
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Fix missing "last" pin connection when using connect_to_pads
When using connect_to_pads on full AXI interface the "last" pin was not connected because of this typo.
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2022-03-24 15:37:59 +04:00 |
enjoy-digital
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ef6d450820
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Merge pull request #1249 from enjoy-digital/setup_fix
Fix litex_setup.py and use local version on CI.
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2022-03-24 10:59:44 +01:00 |
Florent Kermarrec
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caced992ad
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litex_setup: Remove pip3 install amaranth-yosys.
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2022-03-24 10:33:10 +01:00 |
Florent Kermarrec
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1935a2599f
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workflows/ci: Use local version of litex_setup.
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2022-03-24 10:17:08 +01:00 |
Florent Kermarrec
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72b61155c7
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workflows/ci: Checkout to /usr/litex.
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2022-03-24 10:12:38 +01:00 |
Florent Kermarrec
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41bd8539c3
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setup.py: Remove migen/pythondata-software-compiler-rt (Installed through litex_setup.py).
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2022-03-24 10:06:31 +01:00 |
enjoy-digital
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a3b62c9b95
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Merge pull request #1248 from motec-research/pip_install
litex_setup: change to installing with pip
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2022-03-24 09:53:17 +01:00 |
Andrew Dennison
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3f72cd30b1
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litex_setup: change to installing with pip
fixes: EasyInstallDeprecationWarning: easy_install command is deprecated. Use build and pip and other standards-based tools.
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2022-03-23 11:22:56 +11:00 |
Florent Kermarrec
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dd7a04a5c0
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liblitedram/sdram_leveling_center_module: Do a check after final delay configuration.
On ECP5/DDR3, final configuration does not seem to be done correctly each time.
Add a retry/check mechanism to workaround the issue for now.
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2022-03-22 17:12:50 +01:00 |
Florent Kermarrec
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153f9f3660
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soc_core: Fix l2_size argument handling.
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2022-03-22 11:23:01 +01:00 |
Florent Kermarrec
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f0bd7019cd
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soc/add_jtagbone/add_sdram: Add/Use name parameter.
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2022-03-22 09:53:48 +01:00 |
Florent Kermarrec
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e227f3b038
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soc: Improve logs on add_controller, add_csr_bridge and add_cpu.
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2022-03-22 09:41:20 +01:00 |
Florent Kermarrec
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33d6c3de8f
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builder/soc_core: Add missing title.
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2022-03-21 18:07:34 +01:00 |
Florent Kermarrec
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901428f5a9
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soc/add_ethernet: Fix add_ethernet.
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2022-03-21 18:03:40 +01:00 |
Florent Kermarrec
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be23a059ff
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soc/interconnect/csr/CSRConstant: Add constant attribute.
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2022-03-21 18:03:15 +01:00 |
Florent Kermarrec
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4a5ce77d40
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build/soc/cpu parser: Improve titles.
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2022-03-21 17:53:30 +01:00 |
enjoy-digital
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1e6e9777e2
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Merge pull request #1245 from developandplay/demo-fix
Fix compilation of demo.bin on Rocket
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2022-03-21 17:15:59 +01:00 |
Florent Kermarrec
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1583cc8a40
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cpu/naxriscv: Add default value to xlen argument.
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2022-03-21 17:14:24 +01:00 |
Florent Kermarrec
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8e440dc9ea
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soc/integration: Add LiteXSocArgumentParser to be able to expose CPU parameters to user on targets.
Currently used for CPU parameters could problably be extented to simplify other parts
of the code in the future.
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2022-03-21 16:57:14 +01:00 |
Florent Kermarrec
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6ef96b17bc
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soc/interconnect/csr: Fix CSRConstant read method (And add test_csr_constant to test_csr).
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2022-03-21 15:21:08 +01:00 |
Dolu1990
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f5d4977dde
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Merge pull request #1246 from gsomlo/gls-memtest-cast-warning
bios/memtest: fix cast warning
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2022-03-20 21:09:36 +01:00 |
Gabriel Somlo
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e5a2305269
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bios/memtest: fix cast warning
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2022-03-20 14:30:16 -04:00 |
developandplay
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884ee45c28
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Fix compilation of demo.bin on Rocket
- Adjust memory model to fix `relocation truncated` errors
- Make isr.c shared between BIOS and demo to resolve dep on `plic_init`
Based on: https://github.com/enjoy-digital/litex/issues/1168
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2022-03-20 15:39:13 +01:00 |
Dolu1990
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f565bec7f1
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cpu/naxriscv fix xlen not being hashed, improve RV64 performances
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2022-03-18 15:39:58 +01:00 |
Florent Kermarrec
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58549834ec
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tools/litex_sim: Use new get_boot_address function.
Allow litex_sim to use similar .json files than the ones used on hardware.
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2022-03-17 17:46:27 +01:00 |
Florent Kermarrec
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4036c75600
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integration/common: Add get_boot_address to get CPU boot address from json file.
Will allow litex_sim to use similar .json files than the ones used on hardware.
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2022-03-17 17:45:30 +01:00 |
Florent Kermarrec
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dd7709ed6f
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tools/litex_sim/add_sdram: origin no longer required.
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2022-03-17 16:47:02 +01:00 |
Florent Kermarrec
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05724d9fea
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cpu/naxriscv/vexriscv_smp: Declare/Add OpenSBI region in add_soc_compoents.
Avoid doing it in Linux-on-LiteX-Vexriscv.
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2022-03-17 16:28:25 +01:00 |
Florent Kermarrec
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b4db2a3ef2
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tools/litex_sim: Remove obsolete max_sdram_size parameter.
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2022-03-17 16:14:26 +01:00 |
Florent Kermarrec
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3b4a885366
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cpu/naxriscv/vexriscv_smp: Also enforce UART/Timer0 IRQs.
Avoid doing it in Linux-on-LiteX-Vexriscv and allow generating bitstreams directly from litex-boards.
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2022-03-17 16:10:34 +01:00 |
Florent Kermarrec
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e6e3a909f2
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cpu/vexriscv_smp: Set UART/Timer0 CSRs as done on NaxRiscv to ensure OpenSBI compatibility.
This also allow generating bitstreams for Linux-on-LiteX-VexRiscv directly from litex-boards.
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2022-03-17 16:00:05 +01:00 |
Florent Kermarrec
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2ec0ebe40f
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build/gowin: Add copy of bitstream to from impl to gateware directory.
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2022-03-17 09:35:34 +01:00 |
Florent Kermarrec
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148324862a
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integration/builder: Add get_bios_filename/get_bitstream_filename methods to simplify targets/projects.
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2022-03-17 09:19:41 +01:00 |
Florent Kermarrec
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e6a81ec2af
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integration/soc/add_etherbone: Set default buffer_depth to 16 (Allow LiteScope's width up to 512-bit).
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2022-03-16 16:43:28 +01:00 |
Florent Kermarrec
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371608712f
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litex_client: Add CSR Filter.
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2022-03-16 10:59:47 +01:00 |
Florent Kermarrec
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488a6d7256
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litex_client/gui: Minor changes.
- By default, always on top.
- Update register on enter.
- Add title to viewport.
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2022-03-16 09:39:04 +01:00 |
Florent Kermarrec
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1b128804ae
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tools/litex_client: Add initial and very simple GUI support.
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2022-03-15 19:19:01 +01:00 |
Dolu1990
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4896527e6f
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cpu/naxriscv fix git and add RV64 support (--xlen 64)
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2022-03-15 11:54:28 +01:00 |
enjoy-digital
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7712c8a79f
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Merge pull request #1236 from gregdavill/trellis_compress_default
build/trelis: Compress bitstream by default
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2022-03-11 21:56:41 +01:00 |
Florent Kermarrec
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43cc2ff9bb
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software/libbase/memtest: Skip memtest_addr when size < 16KB.
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2022-03-11 15:28:34 +01:00 |
Florent Kermarrec
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c851e74e09
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README: Add link to new LiteX quick tour/overview presentation.
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2022-03-10 18:13:44 +01:00 |
Florent Kermarrec
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1ebcc03a92
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soc/add_pcie: Add address_width support for 64-bit addressing.
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2022-03-10 16:09:18 +01:00 |
Greg Davill
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3de88c1aed
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build/trelis: Compress bitstream by default
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2022-03-10 13:51:14 +10:30 |
Florent Kermarrec
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f446415f68
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cpu/minerva: nMigen -> Amaranth.
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2022-03-09 11:00:50 +01:00 |
Florent Kermarrec
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9d5bf70cb2
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cpu/femtorv/firev: Remove debug displays now that validated in sim and hardware.
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2022-03-09 10:54:05 +01:00 |
Florent Kermarrec
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ece286b15d
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litex_setup: Rename --status to --freeze and generate freezed git_repos dict.
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2022-03-08 18:12:11 +01:00 |