9f75c73d6b
build/xilinx/common: Fix Ultrascale SDROutput/Input.
2021-09-21 10:30:36 +02:00
233f0fc5f4
Merge pull request #1039 from tcal-x/rm-response-ok
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Remove rsp_payload_response_ok from Vex/CFU hookup code.
2021-09-21 09:43:15 +02:00
08779202f4
build/DDRTristate: Fix inconsistencies with SDRTristate (o/i swap).
2021-09-21 08:18:06 +02:00
1be449d72b
Remove rsp_payload_response_ok from Vex/CFU hookup code.
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The port has already been removed from VexRiscv (issue #1036 ).
Signed-off-by: Tim Callahan <tcal@google.com>
2021-09-20 15:02:51 -07:00
1e24fd87d1
cores/gpio: Simplify #1035 .
2021-09-20 17:34:46 +02:00
6251474b39
Merge pull request #1035 from lschuermann/dev/litex-sim-gpio
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litex_sim: optionally add GPIOTristate core
2021-09-20 17:21:29 +02:00
0daa86a8bb
Merge pull request #1038 from antmicro/crosslinknx-ddr-tristate
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build/lattice: add DDRTristate for Crosslink-NX
2021-09-20 14:14:40 +02:00
49d8000d49
gowin/common: Add Differential Input/Output support.
2021-09-20 14:14:06 +02:00
9c373242af
gowin: Add HyperRAM integration hack to match Gowin EDA expected pattern.
2021-09-20 11:47:32 +02:00
6c0a758468
Added syn_useioff attribute support for Oxide toolchain and for the DDRTristate in Crosslink NX
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2021-09-20 11:02:01 +02:00
5519d908e8
cores/video: Rename VideoECP5HDMIPHY to VideoHDMIPHY since in fact generic and can be used on other FPGAs (ex Tang Nano 4k).
2021-09-20 09:29:05 +02:00
4fe085cc1c
cores/clock: Add initial GW1NSR's PLL support.
2021-09-20 08:39:25 +02:00
76c782c546
inetgration/builder: Check for full software re-build only when a CPU is used.
2021-09-20 08:31:22 +02:00
46cd9c5a5c
tools: Minor #1030 cleanups.
2021-09-17 14:37:48 +02:00
8ccb1a91c9
build/openfpgaloader/flash: Add external parameter to allow flashing external SPI Flash when available.
2021-09-17 14:37:14 +02:00
24f0432253
Merge pull request #1030 from teknoman117/fix-lxserver-pcie-crossover
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Fixes to allow crossover uart over PCIe with lxterm and litex_server
2021-09-17 14:28:25 +02:00
a7c9e4ed42
Merge pull request #1033 from caverar/patch-1
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Linker fix for initialized global variables
2021-09-17 14:23:44 +02:00
7f8e2e39f3
cores/video/VideoECP5HDMIPHY: Allow pn_swap on data lanes.
2021-09-16 18:56:05 +02:00
e8e14d8ca5
build/lattice: add DDRTristate for Crosslink-NX
2021-09-16 14:23:02 +02:00
beb7cc691d
CHANGES: Do 2021.08 release.
2021-09-15 15:05:47 +02:00
343d88e837
setup.py: Expose litex_contributors tool.
2021-09-15 14:38:45 +02:00
05b960d09b
CHANGES: Update.
2021-09-15 12:08:30 +02:00
02896a4a30
Merge pull request #1037 from thirtythreeforty/ecp5-pll
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Fix premature selection of full PLL config with no feedback
2021-09-15 08:52:59 +02:00
91ec6e0da8
clock/lattice_ecp5/ECP5PLL: emit frequency annotations to help Diamond
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Unlike nextpnr, Diamond appears not to infer the frequency of the
outputs. Emit the same attributes that Diamond's PLL tool does.
2021-09-15 00:07:43 -05:00
6733a3e3e6
clock/lattice_ecp5/ECP5PLL: ensure feedback path selected before exiting search
2021-09-15 00:07:43 -05:00
88d302d4db
soc/alloc_region: Ensure allocated Region is aligned on size.
2021-09-14 18:08:07 +02:00
694878a35a
integration/soc/add_ethernet/etherbone: Add with_timing_constraints parameter to allow disabling constraints.
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Some boards require specific constraints, so disable them in this case and put constraints in the target file.
2021-09-13 19:32:50 +02:00
8670ac4902
litex_sim: add optional GPIOTristate core
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Adds a switch `--with-gpio`, which will add a 32 pin GPIOTristate
core, with the GPIOTristate signals exposed on the top-level
module. This can be used to add a custom GPIO module in the Verilated
simulation.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 12:33:41 +02:00
cb7b0f44cf
tools/litex_sim: Fix mem_map.
2021-09-13 11:33:16 +02:00
af8459301c
litex/soc/cores/gpio: support external tristate buffer
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Support exposing tristate GPIOs with tristate pads, by avoiding
instantiation of tristate buffers directly in the module. This gives
the developers more flexibility in how they want to implement their
tristate IOs (for example with level shifters behind the IOs), and
allows to use the GPIOTristate core in the Verilated simulation as
Verilator does not support top-level inout signals.
Signed-off-by: Leon Schuermann <leon@is.currently.online>
2021-09-13 11:17:54 +02:00
a235eaf0cd
Linker fix for initialized global variables
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I found that in some cases, initialized global variables don't work with user libraries, so a little change to the linker that I use, taken from the demo file, seems to solve the problem . I think that make more sense to put the global variables in sram and initial values in the main_ram, similar to the bios linker.
2021-09-13 00:44:30 -05:00
9ec45181dd
.gitignore: ignore visual studio code settings
2021-09-08 18:06:45 -07:00
ab3d7e86f2
litex/tools: add command line options and fixes for lxterm to allow crossover uart over PCIe
2021-09-08 18:06:12 -07:00
e0e9311ceb
interconnect/wishbone: Specify Wishbone version ( #999 ).
2021-09-08 17:33:01 +02:00
6c2bc02323
build/xilinx/vivado: Add XilinxVivadoCommands for pre_synthesis/placement/routing_commands with add method to automatically resolve LiteX signals'names.
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This makes it similar to add_platform_command and add more flexibility to constraint the design.
2021-09-08 16:14:58 +02:00
0222697f21
liblitespi/spiflash: Move memspeed to specific function (spiflash_memspeed) and reduce test size.
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On slow configurations (ex iCEBreaker / SERV CPU / 12MHz SPI Flash freq) memspeed test was
too slow (>200s to do the random test for 1MB), so reduce test size to 4KB.
This will be less accurate but will still provide representative results which
is the aim of this test.
2021-09-08 09:10:21 +02:00
10c4523c32
soc/add_spi_flash: Add rate parameter to select 1:1 SDR or 1:2 DDR PHY.
2021-09-07 15:09:05 +02:00
575af6fc60
litespi/integration: Review/Cleanup #1024 .
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Integration from #1024 was working on some boards (ex Arty) but breaking others (ex iCEBreaker);
simplify things for now:
- Avoid duplication in spiflash_freq_init.
- Avoid passing useless SPIFLASH_LEGACY flag to software (software can detect it from csr.h).
- Only keep integration support for "legacy" PHY, others are not generic enough and can be passed with phy parameter.
2021-09-07 14:36:13 +02:00
aff2aefa72
Merge pull request #1024 from antmicro/litespi_refactor
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litex: adding litespi to simulation, making litespi compatible with new implementation
2021-09-07 13:17:40 +02:00
bdd4717daa
Merge pull request #1028 from wuhanstudio/fix-syntax-error
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fix: missing colon syntax error
2021-09-07 13:00:48 +02:00
5d9880888c
fix: missing colon syntax error
2021-09-07 11:21:41 +01:00
a6f9ac58bb
build/sim/common: Review/Cleanup #1021 for consistency with other backends.
2021-09-07 09:44:43 +02:00
2b700057b7
Merge pull request #1021 from antmicro/ddr_sim
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litex: Enable simulation of DDR IO by adding oddr/iddr/ddrtristate simulation models.
2021-09-07 09:38:14 +02:00
7c50f52a57
tools/litex_sim: Improve RAM/SDRAM integration and make closer to LiteX-Boards targets.
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litex_sim: SoC without RAM/SDRAM.
litex_sim --integrated-main-ram-size=0x1000: SoC with RAM of size 0x1000.
litex_sim --with-sdram: SoC with SDRAM.
litex_sim --integrated-main-ram-size=0x1000 --with-sdram: SoC with RAM (priority to RAM over SDRAM).
2021-09-07 09:27:51 +02:00
1598b5958d
Merge pull request #1017 from asadaleem-rs/master
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customize main ram size from command line argument
2021-09-07 09:15:55 +02:00
e257d91d46
cpu/vexriscv: Review/Cleanup #1022 .
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Use CPU_HAS_DCACHE/ICACHE vs CPU_NO_DCACHE/ICACHE for consistency with other software flags.
2021-09-07 09:04:47 +02:00
6b792dce54
Merge pull request #1022 from tcal-x/vex-dcache
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Restructure config flags for dcache/icache presence in Vex.
2021-09-07 08:46:03 +02:00
bafe32dd13
Merge pull request #1020 from shenki/binutils-fixes
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Binutils fixes
2021-09-06 17:16:56 -07:00
ad0fcc22e6
litex: adding legacy mode for litespi
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Inside the litex add_spi_flash function
we are detecting the devices that can't be used with
more efficient DDR version of litespi phy core
and we are choosing whether to instantiate the legacy or DDR core
2021-09-03 09:42:41 +02:00
fa5fd765a4
interconnect/packet: Add dummy to omit list, fixes #1018 .
2021-09-02 18:02:16 +02:00
Andwer E Wilson
enjoy-digital
Tim Callahan
Maciej Kurc
Pawel Sagan
George Hilliard
Leon Schuermann
Camilo Andres Vera Ruiz
Nathaniel R. Lewis
wuhanstudio
Tim Ansell