a03013e427
ci: Bump to ubuntu 20.04.
2022-10-14 18:21:19 +02:00
24cfbd8d67
build/efinity: Update to 2022.1.226.
2022-10-14 10:25:44 +02:00
84db6a0b3a
interconnect/axi: Add AXI version to AXIInterface (default to AXI4) and handle AXI3/AXI4 differences.
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- Max burst length of 16 in AXI3, 256 in AXI4.
- No WID in AXI4.
2022-10-13 11:04:00 +02:00
a8070051b5
cpu/microwatt: Switch to VHD2VConverter to simplify code.
2022-10-13 09:23:20 +02:00
3e23ad3cff
build/vhd2v_converter: Fix add_sources (to make it similar to platform.add_sources).
2022-10-13 09:12:58 +02:00
808cf1a466
Merge pull request #1460 from enjoy-digital/neorv32_params
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cpu/neorv32/core: Avoid configure_litex_core_complex by passing param…
2022-10-12 21:18:14 +02:00
74ae18ddaa
cpu/neorv32/core: Avoid configure_litex_core_complex by passing params to new VHD2VConverter.
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Parameters are passed to Yosys to configure them at the top level before VHDL->Verilog conversion.
2022-10-12 14:47:28 +02:00
efdc9ecef9
build/vhd2v_converter: Always do params -> constants translation.
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Useful when instance is done in the code but params are just passed to VHD2VConverter.
2022-10-12 14:35:43 +02:00
03a5f16d70
build/vhd2v_converter: Add list of things to check.
2022-10-12 12:07:41 +02:00
00f29a3497
build: Rename VHDLWrapper to VHD2VConverter (more explicit).
2022-10-12 11:57:27 +02:00
848245bf59
build/sim/verilator: Add missing support_mixed_language property.
2022-10-12 11:49:42 +02:00
c700f9d0ef
Merge pull request #1453 from trabucayre/vhdl_wrapper
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Vhdl wrapper
2022-10-12 11:42:51 +02:00
bf1349bd17
Merge pull request #1458 from antmicro/rowhammer-etherbone-retry
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Added retransmission logic for EtherBone UDP reads.
2022-10-12 11:27:43 +02:00
ac3699770c
interconnect/stream/ClockDomainCrossing: Expose buffered parameter.
2022-10-06 18:30:02 +02:00
75bf668883
Merge pull request #1450 from tpwrules/improve-intel-pll-calculation
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soc/cores/clock: improve Intel PLL calculation
2022-10-06 12:06:58 +02:00
b47ebf2ce7
Merge pull request #1449 from tpwrules/fix-quartus-clock-constraints
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build/altera: fix clock constraints
2022-10-06 11:59:31 +02:00
536e24f715
soc/cores/cpu/neorv32: convert to VHDLWrapper
2022-10-05 14:10:45 +02:00
8eef2cda0d
build/VHDLWrapper: adding a class to factorize VHDL handling
2022-10-05 14:09:06 +02:00
aa17c27eb9
interconnect/axi/axi_stream: Add clock_domain parameters.
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Useful for wrapping IP and do checks or decide if CDC has to be inserted.
2022-10-05 11:07:34 +02:00
fea73d932e
soc/cores/clock/intel: speed up PLL config computation
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Caching the list of clock divisors to test speeds up computation by
about a factor of three.
2022-10-01 13:08:16 -05:00
b7ef989963
soc/cores/clock/intel_*: respect PFD input frequency
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Only use input clock divisors which respect the device limitation for
the phase-frequency detector's input frequency. This avoids errors where
Quartus complains the PLL parameters are invalid and refuses to
implement it.
The supported PFD frequencies in integer mode have been verified against
each family's datasheet. The unsupported-by-LiteX fractional frequency
information is removed for clarity.
As a bonus, this speeds up PLL config computation by several times.
2022-10-01 13:00:24 -05:00
d89d6dfd0a
soc/cores/clock/intel_common: cleanup
2022-10-01 12:28:32 -05:00
d531a07719
build/altera: fix clock constraints
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This fixes two issues that prevented clock constraints (e.g.
"add_false_path_constraint") from working properly in Quartus.
The first fix passes the "keep" synthesis attribute through to the
generated Verilog in a way Quartus can understand.
The second fix tells Quartus to name PLL clocks according to their net
instead of the physical pin name by passing the "use_net_name" flag to
"derive_pll_clocks" in the .sdc file. Combined with the above, PLL
clocks will now be named according to the kept net.
This fix has been verified on Quartus Prime Lite 20.1.1.720.
2022-09-30 23:33:52 -05:00
3836e8a36c
Merge pull request #1447 from enjoy-digital/naxriscv-merge
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cpu/naxriscv reduce memory latency on peripheral accesses
2022-09-30 16:21:23 +02:00
43699f2768
interconnect/axi/axi_common: Add missing param signals from connect_to_pads.
2022-09-30 14:36:46 +02:00
c9f669d4ec
Merge branch 'master' into naxriscv-merge
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# Conflicts:
# litex/soc/cores/cpu/naxriscv/core.py
2022-09-30 13:37:03 +02:00
79392e6eb8
soc/cores/jtag/Efinix: Cosmetic cleanups and rename EFINIX_JTAG to EfinixJTAG.
2022-09-30 13:34:00 +02:00
b5b820b27f
Merge pull request #1446 from enjoy-digital/vexriscv-smp-merge
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Add Efinix JTAG support, with vexriscv-smp binding function
2022-09-30 13:17:13 +02:00
622a35fd4e
Improve naxriscv peripheral latency
2022-09-30 11:52:14 +02:00
cb0e9c23d3
Add Efinix JTAG support, with vexriscv-smp binding function
2022-09-30 11:48:07 +02:00
af58237203
software/demo: Add comments for Nix specific changes (To ease future maintenance and avoid breaking it).
2022-09-29 17:30:09 +02:00
1fb1cf19e5
Merge pull request #1434 from tpwrules/fix-bare-metal-demo
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demo: fix minor build issues
2022-09-29 17:20:12 +02:00
c5eaac9c3e
build/xilinx/vivado: Cosmetic cleanup.
2022-09-29 17:16:16 +02:00
28fb3962df
Merge pull request #1444 from cklarhorst/more_vivado_options
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Vivado: Make directives configurable via argparser
2022-09-29 17:12:44 +02:00
ad8b7da63d
Merge pull request #1442 from trabucayre/video_swap_blue_red
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soc/cores/video: swap red and blue channel
2022-09-29 17:04:09 +02:00
8ffdc535d1
Vivado: Make directives configurable via argparser + add option to limit vivado threads
2022-09-29 15:42:15 +02:00
dc0a4ea40b
soc/cores/video: swap red and blue channel
2022-09-27 08:07:31 +02:00
c717e4c824
Merge pull request #1440 from cklarhorst/naxriscv
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Naxriscv: Add two more argparser options for devs
2022-09-26 12:48:47 +02:00
9c43fe85c6
cpu/naxriscv: Add --no-netlist-cache
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Ignores the netlist cache.
When you hack on naxriscv code, you always want fresh results.
2022-09-25 21:00:03 +02:00
7795fba3cf
cpu/naxriscv: Add --update-repo option & check for update errors
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Allows different update strategies which I find useful.
The git update process now checks the return code! So that problems in the update process can be noticed.
2022-09-25 20:51:37 +02:00
759530f272
build/generic_platform, generic_toolchain, yosys_nextpnr_wrapper: introduce the information about ability to do synthesis with mixed languages
2022-09-23 19:02:48 +02:00
b8e22fcd79
interconnect/axi: Simplify/Fix IOs generation. (Param signals were missing for AXIFull).
2022-09-22 09:54:58 +02:00
162a0a4c1e
cpu/rocket: fix variant typos
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The `fulld` and `fullq` variants point to the wrong (`LitexFullConfig`)
verilog. Fix by pointing to the correct code (`LitexFullDConfig` and
`LitexFullQConfig`, respectively).
Reported-by: Ioannis Ioannou <roryt@roryt.gr>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-09-20 09:29:46 -04:00
cb8e0193fc
Added retransmission logic for EtherBone UDP reads.
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Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2022-09-20 09:26:24 +02:00
e12af4f050
interconnect/axi/axi_stream: Fix get_ios and base it on length of created Endpoint's signals.
2022-09-20 09:08:22 +02:00
23db2e65f4
Merge pull request #1437 from trabucayre/yosys_nextpnr_refactor_args
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build/yosys,nextpnr, lattice: refactor args
2022-09-19 19:29:34 +02:00
e9f6642d8f
build/yosys,nextpnr, lattice: refactor args
2022-09-19 19:08:25 +02:00
32272ba855
axi/axi_stream: Set default keep_width to None and automatically set it to data_width//8 when not specified.
2022-09-19 13:28:42 +02:00
860c757f33
Merge pull request #1435 from gsomlo/gls-yosys-flow3
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yosys_nextpnr_toolchain: add flow3 option to abc9 mode
2022-09-19 09:18:00 +02:00
441042bef4
yosys_nextpnr_toolchain: add flow3 option to abc9 mode
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Add "flow3" option to abc9 mode. This runs FPGA mapping several times,
producing a generally better mapping at the cost of increased runtime
(see https://github.com/Ravenslofty/yosys-cookbook/blob/master/ecp5.md ).
Also, add a "--yosys-flow3" build option to both "trellis" and "oxide".
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2022-09-18 08:28:40 -04:00
Florent Kermarrec
Gwenhael Goavec-Merou
Thomas Watson
Dolu1990
Christian Klarhorst
Gabriel Somlo
Maciej Kurc