Commit Graph

9069 Commits

Author SHA1 Message Date
enjoy-digital b8dc1b7757
Merge pull request #1738 from trabucayre/fix_toolchain
litex_setup: fix software build when liteeth or/and litesata is set (riscv toolchain issue)
2023-07-31 08:57:52 +02:00
Gwenhael Goavec-Merou 1a74854e55 litex_setup: fix software build when liteeth or/and litesata is set (riscv toolchain issue) 2023-07-30 15:37:51 +02:00
Florent Kermarrec b2e4b22145 soc/add_pcie: Add with_ptm parameter and update CHANGES. 2023-07-30 15:12:01 +02:00
rowanG077 91e1e53662 soc/interconnect/stream: BufferizeEndpoints params
BufferizeEndpoints params now includes parameters which to pipeline
    the valid/data or ready path
2023-07-30 00:24:26 +02:00
Florent Kermarrec ff67781f11 interconnect/axi/axi_common: Document constants. 2023-07-28 09:26:53 +02:00
Florent Kermarrec ff18374c52 interconnect/axi/axi_common: Document helper functions. 2023-07-28 09:15:52 +02:00
Florent Kermarrec 717fb131fd interconnect/axi: Switch to LiteXModule. 2023-07-28 09:15:22 +02:00
Florent Kermarrec ed12f8787d litex/gen: Add some comments. 2023-07-27 16:18:30 +02:00
Florent Kermarrec 095cfb7811 litex/gen: Split common in common/context/reduce/signal. 2023-07-27 15:02:37 +02:00
Florent Kermarrec 74401d6f03 CHANGES: Update. 2023-07-27 13:58:45 +02:00
Florent Kermarrec bbf944c3ba build/efinix/efinity: Fix build with 2023.1. 2023-07-27 13:55:27 +02:00
Florent Kermarrec 924da55ea0 stream/AsyncFIFO: Add a minimum of 2 buffers on Efinix FPGAs to fix issues on hardware.
Root cause still need to be understand, but when testing with another AsyncFIFO (from verilog axis),
the behavior was similar. So is it an Efinity issue? Constraint issue?
2023-07-27 13:29:05 +02:00
Florent Kermarrec 72a1592bee litex/gen: Add initial/minimal LiteXContext to easily get build context from modules.
Still a PoC and need to think a bit more about it, but will allow fixing AsyncFIFO issue
on Efinix FPGAs.
2023-07-27 13:27:15 +02:00
Florent Kermarrec 20ce982da2 software/bios: Fix missing CSR_SDCARD_CORE_BASE update. 2023-07-26 16:30:52 +02:00
Florent Kermarrec 66b44ecd60 soc/add_uart: Fix stub behavior (sink/source swap), thanks @zyp. 2023-07-26 12:26:16 +02:00
Florent Kermarrec 0f1fdea893 build/xilinx/vivado: Also generate design checkpoint after synthesis and placement.
This help exploring/constraining complex designs by using Vivado GUI and design checkpoint.
2023-07-21 19:53:28 +02:00
Florent Kermarrec 35cd744adc CHANGES: Update. 2023-07-21 15:16:42 +02:00
Florent Kermarrec 330d61d2bd soc/add_pcie: Remove MSI workaround on Ultrascale(+) now that root cause is understood/fixed (thanks @smunaut). 2023-07-21 14:50:38 +02:00
Florent Kermarrec aae15737cd CHANGES: Update. 2023-07-20 16:30:48 +02:00
Florent Kermarrec c00f61d9d7 tools: Update to new sdcard core name. 2023-07-20 16:29:05 +02:00
Florent Kermarrec 6693a723d1 software: Update to new sdcard core name. 2023-07-20 16:28:51 +02:00
Florent Kermarrec 0152e7de8e soc/add_sata: Use name parameter to allow multiple sdcard instances. 2023-07-20 16:28:22 +02:00
Florent Kermarrec e364316814 soc/add_sata: Use name parameter to allow multiple sata instances. 2023-07-20 16:02:03 +02:00
Florent Kermarrec f995d74e55 soc/add_uartbone: Rename name parameter to uart_name to allow multiple uartbone (also for consistency with other cores) and other minor cleanups. 2023-07-20 15:42:03 +02:00
Florent Kermarrec 6e78db6767 soc/add_bus_master: Use name where possible to avoid automatic naming and improve log readability. 2023-07-20 15:15:44 +02:00
Florent Kermarrec f6da67fb38 soc/add_pcie: Add optional data_width parameter. 2023-07-20 10:35:10 +02:00
Florent Kermarrec 69c6fa11d2 build/lattice/common/lattice_ecp5_trellis_special_overrides: Add missing DifferentialOutput. 2023-07-17 17:08:35 +02:00
Florent Kermarrec 6ab156e225 soc/cores: Fix regressions. 2023-07-17 11:48:39 +02:00
Florent Kermarrec 79a82dc732 tools/litex_json2dts_linux: Remove duplicated clock definition.
Keep clock definition introduced by 9b67898e99.
2023-07-17 11:27:07 +02:00
Florent Kermarrec 3d101b9749 integration/export: When csr_base is specified, make CSR regions definition relative to it.
Useful for PCIe based systems when internal CSR base is automatically added by the logic.
2023-07-17 11:14:33 +02:00
Florent Kermarrec 3fc16f54f1 soc/cores/cpu: Switch to LiteXModule. 2023-07-17 09:26:58 +02:00
Florent Kermarrec 39ff69ade7 cores/spi: Switch to LiteXModule. 2023-07-17 09:14:47 +02:00
Florent Kermarrec 028f7eb72f cores/ram: Switch to LiteXModule. 2023-07-17 09:12:25 +02:00
Florent Kermarrec b35c6580e8 soc/cores/clock: Switch to LiteXModule. 2023-07-15 21:54:07 +02:00
Florent Kermarrec 8103cf7851 soc/cores: Switch cores to LiteXModule (still need to do cpu, ram, clk, spi). 2023-07-14 22:19:14 +02:00
Florent Kermarrec 6e46710678 gen/fhdl/module: Fix CSR clock domain renaming to cores converted to LiteXModule, thanks @smunaut. 2023-07-14 10:01:32 +02:00
Dolu1990 987a35e1ec
Merge pull request #1729 from riktw/master
Currently using a lite or minimal Vexriscv config with debug and brea…
2023-07-13 15:21:51 +02:00
Florent Kermarrec 3a2586c48b soc/add_pcie: Remove csr_ordering parameter (not useful and remove on litepcie). 2023-07-12 19:42:54 +02:00
Florent Kermarrec f9e32eb3eb CHANGES: Update. 2023-07-11 16:42:21 +02:00
riktw eb1afbad47 Currently using a lite or minimal Vexriscv config with debug and breakpoints throws an error. Updated the GCC_FLAGS to include these two variants as well. 2023-07-11 16:16:51 +02:00
Florent Kermarrec 26732f626f CHANGES: Update. 2023-07-10 11:24:49 +02:00
Florent Kermarrec d18c6316f4 gen/fhdl/verilog: Improve signal sort by name instead of duid to improve reproducibility. 2023-07-10 11:24:46 +02:00
enjoy-digital 698b4dd875
Merge pull request #1728 from stone3311/master
cores/arm: Fix computed goto in boot helpers
2023-07-10 08:31:07 +02:00
stone3311 42c422e767 cores/arm: Fix computed goto in boot helpers 2023-07-09 19:16:06 +02:00
Florent Kermarrec e62f51c3eb gen/genlib/cdc: Add missing import. 2023-07-07 11:51:04 +02:00
Florent Kermarrec 2b941cdcd9 gen/genlib: Add copy of genlib.cdc modules that we are using and not supported by Amaranth to prepare #1727. 2023-07-06 22:23:54 +02:00
Florent Kermarrec e9739b5446 soc: Switch to litex.gen.genlib.misc. 2023-07-06 22:05:23 +02:00
Florent Kermarrec 6f98053b1a litex/gen: Add copy of genlib.misc to prepare for #1727. 2023-07-06 22:03:41 +02:00
Gwenhael Goavec-Merou ec43ca77ed
Merge pull request #1724 from stone3311/master
cores/zynqmp: Fix boot helper
2023-07-06 09:15:13 +02:00
stone3311 54f466772b cores/zynqmp: Fix boot helper 2023-07-05 20:14:05 +02:00