Florent Kermarrec
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b031c5edae
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targets: fix MiniSoC
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2015-02-27 17:12:37 +01:00 |
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Florent Kermarrec
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e07e124118
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sdram: import dfi, lasmibus, wishbone2lasmi from Migen in sdram/bus dir
We will maybe move things, but at least it's in MiSoC now
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2015-02-27 17:07:44 +01:00 |
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Florent Kermarrec
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e82531cdf8
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move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
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2015-02-27 16:54:22 +01:00 |
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Florent Kermarrec
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07b9cabd0d
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gensoc: make it more generic (a SoC does not necessarily have a CPU)
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2015-02-27 16:39:00 +01:00 |
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Florent Kermarrec
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367db268ad
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reserve csr_map 0-->16 for gensoc internal csrs
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2015-02-27 14:18:13 +01:00 |
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Florent Kermarrec
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be0eb8d265
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use cachesize reported in wishbone2lasmi
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2015-02-27 14:13:38 +01:00 |
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Florent Kermarrec
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225a2d4704
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report cachesize in wishbone2lasmi
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2015-02-27 14:12:13 +01:00 |
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Florent Kermarrec
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9814001c79
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create cpu dir and move lm32/mor1kx in it
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2015-02-27 10:51:03 +01:00 |
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Florent Kermarrec
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9f636f7985
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move memtest to sdram
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2015-02-27 10:47:54 +01:00 |
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Florent Kermarrec
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b817cf49b3
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replace self._r_register by self._register in all CSR declaration
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2015-02-27 10:36:09 +01:00 |
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Florent Kermarrec
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e4de5a0c9d
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make.py: avoid some actions in make all (do not flash if load-bitstream is specified or if bios is in blockram)
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2015-02-27 10:23:17 +01:00 |
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Florent Kermarrec
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77a6f580e2
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gensoc: add check_cpu_memory_region and check_csr_region to detect csr and mem regions conflicts
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2015-02-27 10:23:02 +01:00 |
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Florent Kermarrec
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617bc70d7f
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liteeth: move doc
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2015-02-27 09:15:54 +01:00 |
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Florent Kermarrec
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54a8a52e90
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xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...))
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2015-02-27 09:05:23 +01:00 |
Robert Jordens
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2b0937153d
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xilinx/programmer: fix xc3sprog (GenericProgrammer)
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2015-02-26 21:36:15 -07:00 |
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Robert Jordens
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2b12679ef6
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add pipistrello target
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2015-02-26 21:35:42 -07:00 |
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Robert Jordens
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8de5b947bd
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pipistrello: use fpgaprog
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2015-02-26 21:34:02 -07:00 |
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Robert Jordens
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ca52aa5b8c
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add fpgaprog programmer
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2015-02-26 21:33:49 -07:00 |
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Robert Jordens
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5b5d2d15b8
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add pipistrello platform
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2015-02-26 21:33:42 -07:00 |
Sebastien Bourdeauducq
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ba26a400e3
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Merge branch 'master' of https://github.com/m-labs/migen
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2015-02-26 21:32:39 -07:00 |
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Robert Jordens
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c9ed38dec8
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gensoc: missing self.
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2015-02-26 21:32:11 -07:00 |
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Sebastien Bourdeauducq
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a3909bb5e2
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Merge branch 'master' of https://github.com/m-labs/misoc
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2015-02-26 21:28:12 -07:00 |
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Sebastien Bourdeauducq
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28c219ebd2
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platforms/kc705: add user SMA clock
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2015-02-26 16:22:22 -07:00 |
Yann Sionneau
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8364fe6674
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target/kc705: allow access to pll_sys signal before BUFG
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2015-02-26 15:56:10 -07:00 |
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Yann Sionneau
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dbdb263acc
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mibuild/kc705: add missing pins on FMC LPC
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2015-02-26 15:54:41 -07:00 |
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Florent Kermarrec
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09fbbca53e
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gensoc: cpus now directly add their verilog sources
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2015-02-26 20:49:21 +01:00 |
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Florent Kermarrec
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5e8a0c496d
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gensoc: add mem_map and mem_decoder to avoid duplications
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2015-02-26 20:12:27 +01:00 |
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Florent Kermarrec
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5ac5ffe359
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gensoc: get platform_id from platform
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2015-02-26 19:07:19 +01:00 |
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Florent Kermarrec
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8da1faf310
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mibuild: move identifier to platforms
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2015-02-26 19:00:43 +01:00 |
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Florent Kermarrec
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e6a21b2305
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mibuild: fix missing xilinx_common -->xilinx.common change
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2015-02-26 14:04:36 +01:00 |
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Florent Kermarrec
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554731ae44
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targets/simple: make it generic (no default_platform, use platform's default_clk_name/default_clk_period)
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2015-02-26 13:08:15 +01:00 |
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Florent Kermarrec
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bd5ed0977b
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platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms)
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2015-02-26 12:51:57 +01:00 |
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Florent Kermarrec
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e27a94e7fc
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mibuild: add VivadoProgrammer (only load_bitstream)
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2015-02-26 12:31:19 +01:00 |
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Florent Kermarrec
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b3faf5f0da
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mibuild: better file organization (create directory for each vendor and move programmers in it)
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2015-02-26 12:25:59 +01:00 |
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Florent Kermarrec
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02b3f51382
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liteeth: fix example_designs generation
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2015-02-26 10:23:38 +01:00 |
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Florent Kermarrec
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00862a383c
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liteeth: fix import (from liteeth --> from misoclib.liteeth)
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2015-02-26 09:48:37 +01:00 |
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Florent Kermarrec
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60effe1d95
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move files to liteeeth and create example_designs directory
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2015-02-26 09:35:14 +01:00 |
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Sebastien Bourdeauducq
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0267868cbe
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remove litex submodule
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2015-02-25 10:40:44 -07:00 |
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Sebastien Bourdeauducq
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658cb0e405
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merge liteeth
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2015-02-25 10:35:39 -07:00 |
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Sebastien Bourdeauducq
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8015d12692
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move files for misoc integration
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2015-02-25 10:34:11 -07:00 |
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Florent Kermarrec
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eef679b6d4
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phy/sim: generate sop/eop
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2015-02-25 17:47:44 +01:00 |
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Florent Kermarrec
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a559fc77c8
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remove upload optimization (we will use wishbone later for performance)
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2015-02-24 18:01:04 +01:00 |
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Florent Kermarrec
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6b7026f521
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add sim phy
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2015-02-24 01:42:56 +01:00 |
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Florent Kermarrec
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b6ebcece95
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add read grouping to etherbone, we now have interesting upload speeds... :)
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2015-02-23 18:58:31 +01:00 |
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Florent Kermarrec
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ac5b7c073a
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test: add make.py to replace static config.py file
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2015-02-23 18:55:19 +01:00 |
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Florent Kermarrec
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71f3a5bf13
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prepare reads grouping to speed up upload
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2015-02-23 18:11:08 +01:00 |
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Florent Kermarrec
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e309ba55ea
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use new Migen sel signal to change the way we upload data (will enable fifo bursts)
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2015-02-23 12:34:04 +01:00 |
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Florent Kermarrec
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d3486dba91
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rle: increase dw automatically when needed
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2015-02-23 09:41:18 +01:00 |
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Florent Kermarrec
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2a2c3af380
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host/dump: optimize get_bits / decode_rle since we can now have large dumps
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2015-02-23 02:14:20 +01:00 |
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Florent Kermarrec
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861c54760e
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host/driver/reg: use burst mode to speed up upload of data (useful with Etherbone)
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2015-02-23 00:49:59 +01:00 |