Florent Kermarrec
|
58290f3c43
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lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
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2015-03-01 22:04:20 +01:00 |
|
Florent Kermarrec
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382ca374c3
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mibuild: initial Verilator support
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2015-03-01 18:27:46 +01:00 |
|
Florent Kermarrec
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f58394f6af
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soc: add initial verilator sim support: ./make.py -t simple -p sim build-bitstream :)
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2015-03-01 18:25:47 +01:00 |
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Florent Kermarrec
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4f37d29d05
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flash/spi: make bitbang optional (enabled by default)
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2015-03-01 17:15:22 +01:00 |
|
Florent Kermarrec
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096e95cb59
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uart: use data instead of d on endpoint's layouts (coherency with others cores)
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2015-03-01 16:56:48 +01:00 |
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Florent Kermarrec
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1e6d1deae8
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uart: add sim phy
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2015-03-01 16:52:50 +01:00 |
|
Florent Kermarrec
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649cdeb265
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liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
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2015-03-01 16:48:41 +01:00 |
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Florent Kermarrec
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8f81ae6826
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genlib/misc: add FlipFlop, Counter, Timeout
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2015-03-01 16:33:46 +01:00 |
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Florent Kermarrec
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bd4d3cd73b
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uart: create phy directory and move phy logic to serial.py (will enable selecting uart phy, for example virtual uart with LiteEth or sim model for Verilator)
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2015-03-01 12:14:34 +01:00 |
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Florent Kermarrec
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9e01bf5fdd
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litesata: create example design derived from SoC
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2015-03-01 11:33:38 +01:00 |
|
Florent Kermarrec
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c21a7956c8
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liteXXX cores: remove Identifier duplication
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2015-03-01 11:24:58 +01:00 |
|
Florent Kermarrec
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67ca0da1d9
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liteXXX cores: share same methodology for on-board tests
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2015-03-01 11:21:12 +01:00 |
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Florent Kermarrec
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7b464b2b1c
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litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
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2015-03-01 11:03:15 +01:00 |
|
Florent Kermarrec
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32fce11edf
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litescope: avoid uart code duplication
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2015-03-01 10:07:55 +01:00 |
|
Florent Kermarrec
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1b7f8d0439
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video: reintegrate dvisampler from mixxeo (DVI/HDMI interfaces are common in today's SoCs)
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2015-03-01 10:07:52 +01:00 |
Sebastien Bourdeauducq
|
961b4bfb4c
|
platforms/pipistrello: remove unconnected SDRAM pins
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2015-02-28 16:20:44 -07:00 |
Robert Jordens
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93b80b2f1c
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pipistrello: fix lpddr parameters, crg, flash, style
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2015-02-28 16:17:34 -07:00 |
|
Robert Jordens
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03431ece9f
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pipistrello: fix ddram dqs, cleanup constraints, add pullup/downs
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2015-02-28 16:16:47 -07:00 |
|
Robert Jordens
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75290aa0f3
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pipistrello: switch back to xc3sprog and fast (papilio) speed
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2015-02-28 16:16:47 -07:00 |
|
Florent Kermarrec
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144ee7ea9f
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soc: fix register_rom
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2015-02-28 23:51:51 +01:00 |
|
Florent Kermarrec
|
eb8ba145de
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kx705: add programmer parameter
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2015-02-28 23:34:57 +01:00 |
|
Florent Kermarrec
|
b32a0e6f9e
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liteeth: create example design derived from SoC that can be used on all targets with Ethernet pins
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2015-02-28 23:33:00 +01:00 |
|
Florent Kermarrec
|
b34be816ec
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liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
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2015-02-28 22:23:48 +01:00 |
|
Florent Kermarrec
|
5c43d4d091
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litescope: create example design derived from SoC that can be used on all targets
|
2015-02-28 22:19:24 +01:00 |
|
Florent Kermarrec
|
0fd1b9df8d
|
liteXXX cores: remove redefinition of get_csr_csv
|
2015-02-28 21:45:05 +01:00 |
|
Florent Kermarrec
|
5bd1ab7fa1
|
liteXXX cores: update README and doc
|
2015-02-28 21:40:59 +01:00 |
|
Florent Kermarrec
|
165a5b6760
|
soc: use self.cpu_reset_address as rom mem_map address and increase default bios size to 0xa000
|
2015-02-28 20:04:51 +01:00 |
|
Florent Kermarrec
|
b53e2b0d6e
|
fix xilinx/programmer with Vivado
|
2015-02-28 19:33:20 +01:00 |
|
Florent Kermarrec
|
6107b7844a
|
test implementation on all targets and fix issues
|
2015-02-28 12:04:51 +01:00 |
|
Florent Kermarrec
|
1366ff5e26
|
move mxcrg to others (we should integrate it in mlabs_video.py and remove the verilog file in the future)
|
2015-02-28 11:51:51 +01:00 |
|
Florent Kermarrec
|
8564b7eb6a
|
soc: move SDRAMSoC to a separate sdram.py file (ideally part of SDRAMSoC should move mem/sdram)
|
2015-02-28 11:44:14 +01:00 |
|
Florent Kermarrec
|
69e869893d
|
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
|
2015-02-28 11:36:15 +01:00 |
|
Florent Kermarrec
|
912573f5c9
|
liteusb: move files and modify import to misoclib.com.liteusb
|
2015-02-28 11:18:00 +01:00 |
|
Florent Kermarrec
|
b647fe5823
|
merge liteusb
|
2015-02-28 11:16:16 +01:00 |
|
Florent Kermarrec
|
8e67d6e69f
|
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
|
2015-02-28 11:08:17 +01:00 |
|
Florent Kermarrec
|
2c3e8a2804
|
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
|
2015-02-28 11:04:48 +01:00 |
|
Florent Kermarrec
|
0dfca49e68
|
litesata: move file and modify import to misoclib.mem.litesata
|
2015-02-28 11:03:24 +01:00 |
|
Florent Kermarrec
|
b6358be0a1
|
merge litesata
|
2015-02-28 10:48:08 +01:00 |
|
Florent Kermarrec
|
df0ba1b03c
|
litescope: create example_designs directory
|
2015-02-28 10:42:12 +01:00 |
|
Florent Kermarrec
|
c4ebf244a1
|
litescope: move files and modify import to misoclib.tools.litescope
|
2015-02-28 10:33:46 +01:00 |
|
Florent Kermarrec
|
b274e948dc
|
merge litescope
|
2015-02-28 10:24:49 +01:00 |
|
Florent Kermarrec
|
a43c555ee3
|
misoclib/com: add spi (only SPIMaster for now)
|
2015-02-28 09:43:03 +01:00 |
|
Florent Kermarrec
|
2c51adcd68
|
misoclib: better organization (create cores categories: cpu, mem, com, ...)
|
2015-02-28 09:40:44 +01:00 |
|
Florent Kermarrec
|
87d8ff2de7
|
xilinx/programmer: add source of vivado's settings (need to be tested on a linux machine)
|
2015-02-28 03:38:47 +01:00 |
|
Florent Kermarrec
|
6b93849a08
|
gensoc: parameter check is now more restrictive, add additional info to help user
|
2015-02-28 03:12:00 +01:00 |
|
Florent Kermarrec
|
8e04ef7b95
|
test minicon with de0nano (OK) and fix missing self in gensoc
|
2015-02-27 20:00:16 +01:00 |
|
Florent Kermarrec
|
f1200d6388
|
gensoc: move I/O for rom initialization to make.py
|
2015-02-27 19:48:07 +01:00 |
|
Florent Kermarrec
|
074f576340
|
targets: add de0nano (100MHz, integrated bios and SDRAM)
|
2015-02-27 19:47:32 +01:00 |
|
Florent Kermarrec
|
cb38580400
|
make.py fix indent
|
2015-02-27 18:58:36 +01:00 |
|
Florent Kermarrec
|
5e2e9338d2
|
bios: we can now use -Ot with_rom True on targets to force bios implementation in integrated rom (can speed up debug we don't want to reflash SPI or NOR flash)
|
2015-02-27 17:22:44 +01:00 |