Florent Kermarrec
a72c091bc2
mibuild/sim: regroup console_tb/ethernet_tb in dut_tb
2015-03-09 14:40:31 +01:00
Florent Kermarrec
e82b540a96
mibuild/sim: remove server and interact with tap directly in cpp tb. for now: - need to create tap manually: create tap: openvpn --mktun --dev tap0 ifconfig tap0 192.168.0.14 up mknod /dev/net/tap0 c 10 200 delete tap: openvpn --rmtun --dev tap0 - ARP request/reply OK - TFTP request OK - need to be tested with TFTP server. - need clean up
2015-03-09 13:30:21 +01:00
Robert Jordens
3e84c66ba9
vivado: permit resources without pins
...
This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
2015-03-09 13:30:19 +01:00
Florent Kermarrec
e60a97534b
mibuild/sim: able to visualize arp requests with wireshark
...
now need to find why that is not responding...
2015-03-06 20:16:30 +01:00
Florent Kermarrec
a64acdfa65
mibuild/sim: able to send ethernet frame from sim to server.py
2015-03-06 12:49:56 +01:00
Florent Kermarrec
0029b87628
mibuild/sim: add ethernet pins to verilor.py
2015-03-06 12:20:17 +01:00
Florent Kermarrec
658d4d4c49
platforms/sim: add ethernet pins
2015-03-06 10:20:26 +01:00
Sebastien Bourdeauducq
7b00141a0c
genlib/cordic: fix typos
2015-03-06 00:47:23 +01:00
Florent Kermarrec
06f3c46e35
genlib/misc: fix missing *args in Counter
2015-03-04 23:49:15 +01:00
Florent Kermarrec
3d7f9fd685
mibuild/sim/server_tb: use SERIAL_SINK_ACK
2015-03-04 00:55:35 +01:00
Florent Kermarrec
2d6fbd7902
mibuild/sim: use /tmp/simsocket sockaddr for server
2015-03-03 22:52:28 +01:00
Florent Kermarrec
f4b060f6fe
mibuild/sim: avoid updating end at each cycle (simulation speedup)
2015-03-03 18:01:14 +01:00
Florent Kermarrec
5ec26a49c3
mibuild/sim: simplify console_tb with sim struct
2015-03-03 17:57:58 +01:00
Florent Kermarrec
991572f4fe
mibuild/sim: create server.py and server_tb (Proof of concept OK with flterm)
...
Using a server allow us to create a virtual UART (and ethernet TAP in the future).
1) start the server
2) start flterm on the virtual serial port created by the server
3) run the simulation
This will enable us to do serialboot and netboot in simulation.
This will also enable prototyping ethernet for ARTIQ in simulation.
2015-03-03 17:38:22 +01:00
Sebastien Bourdeauducq
f154c2e7ec
xilinx/programmer/vivado: fix Linux support
2015-03-03 02:06:39 +00:00
Sebastien Bourdeauducq
154ad54a8e
platforms/kc705: fix imports
2015-03-03 02:03:14 +00:00
Florent Kermarrec
a56fce045b
Merge branch 'master' of http://github.com/m-labs/migen
2015-03-02 23:24:48 +01:00
Florent Kermarrec
29c5bb8bcd
mibuild/sim/verilator: remove verilator_root, use -Wno-fatal and add verbose option (verbose disabled by default)
2015-03-02 23:23:23 +01:00
Sebastien Bourdeauducq
36f4b68dd8
mibuild/sim: style fixes
2015-03-02 21:56:20 +00:00
Florent Kermarrec
7d68ecbd86
move dma_lasmi to MiSoC
2015-03-02 08:23:02 +01:00
Florent Kermarrec
58290f3c43
lasmi: simplify usage for the user (it's the job of the controller to manage write/read latencies on acks)
2015-03-01 22:04:20 +01:00
Florent Kermarrec
382ca374c3
mibuild: initial Verilator support
2015-03-01 18:27:46 +01:00
Florent Kermarrec
8f81ae6826
genlib/misc: add FlipFlop, Counter, Timeout
2015-03-01 16:33:46 +01:00
Sebastien Bourdeauducq
961b4bfb4c
platforms/pipistrello: remove unconnected SDRAM pins
2015-02-28 16:20:44 -07:00
Robert Jordens
03431ece9f
pipistrello: fix ddram dqs, cleanup constraints, add pullup/downs
2015-02-28 16:16:47 -07:00
Robert Jordens
75290aa0f3
pipistrello: switch back to xc3sprog and fast (papilio) speed
2015-02-28 16:16:47 -07:00
Florent Kermarrec
eb8ba145de
kx705: add programmer parameter
2015-02-28 23:34:57 +01:00
Florent Kermarrec
b53e2b0d6e
fix xilinx/programmer with Vivado
2015-02-28 19:33:20 +01:00
Florent Kermarrec
87d8ff2de7
xilinx/programmer: add source of vivado's settings (need to be tested on a linux machine)
2015-02-28 03:38:47 +01:00
Florent Kermarrec
e82531cdf8
move dfi/lasmibus/wishbone2lasmi to MiSoC sdram
2015-02-27 16:54:22 +01:00
Florent Kermarrec
225a2d4704
report cachesize in wishbone2lasmi
2015-02-27 14:12:13 +01:00
Florent Kermarrec
54a8a52e90
xilinx/programmer: add partial flash_bitstream for vivado (can flash full bitstream, need to be adapted to flash part of the flash (bios, ...))
2015-02-27 09:05:23 +01:00
Robert Jordens
2b0937153d
xilinx/programmer: fix xc3sprog (GenericProgrammer)
2015-02-26 21:36:15 -07:00
Robert Jordens
8de5b947bd
pipistrello: use fpgaprog
2015-02-26 21:34:02 -07:00
Robert Jordens
ca52aa5b8c
add fpgaprog programmer
2015-02-26 21:33:49 -07:00
Robert Jordens
5b5d2d15b8
add pipistrello platform
2015-02-26 21:33:42 -07:00
Sebastien Bourdeauducq
ba26a400e3
Merge branch 'master' of https://github.com/m-labs/migen
2015-02-26 21:32:39 -07:00
Sebastien Bourdeauducq
28c219ebd2
platforms/kc705: add user SMA clock
2015-02-26 16:22:22 -07:00
Yann Sionneau
dbdb263acc
mibuild/kc705: add missing pins on FMC LPC
2015-02-26 15:54:41 -07:00
Florent Kermarrec
8da1faf310
mibuild: move identifier to platforms
2015-02-26 19:00:43 +01:00
Florent Kermarrec
e6a21b2305
mibuild: fix missing xilinx_common -->xilinx.common change
2015-02-26 14:04:36 +01:00
Florent Kermarrec
bd5ed0977b
platforms: add default_clk_freq/default_clk_name (to use it on simple designs to test MiSOC on various platforms)
2015-02-26 12:51:57 +01:00
Florent Kermarrec
e27a94e7fc
mibuild: add VivadoProgrammer (only load_bitstream)
2015-02-26 12:31:19 +01:00
Florent Kermarrec
b3faf5f0da
mibuild: better file organization (create directory for each vendor and move programmers in it)
2015-02-26 12:25:59 +01:00
Yann Sionneau
5bb1c789aa
mibuild/kc705: add FMC connectors
2015-02-18 08:32:45 -07:00
Yann Sionneau
cea1551ae0
mibuild: support pin names in IO extensions
2015-02-18 08:32:31 -07:00
Florent Kermarrec
452c60e0c3
endpoints: add param_layout parameter (required to pass parameter data with converters and will allow logic optimizations)
2015-02-14 03:10:56 -08:00
Florent Kermarrec
319465445d
actorlib/structuring: fix eop generation in Pack
2015-02-14 03:07:18 -08:00
Sebastien Bourdeauducq
d51d33af73
mibuild: make resolve_signals public
2015-02-14 03:05:07 -08:00
Florent Kermarrec
beef7425ce
mibuild: return verilog namespace with build
2015-02-14 03:02:47 -08:00
