a79696641a
prepare identify test with SATACON
2014-12-19 19:05:49 +01:00
880c7e7ecc
test: change UART baudrate and test SATACONTRemover
2014-12-19 17:45:02 +01:00
33eed1aa79
SATAPHYDatapathRX: use Converter and simplify
2014-12-19 17:27:44 +01:00
0ab7ca6f28
SATAPHYDatapathTX: use Converter and simplify
2014-12-19 17:13:03 +01:00
8bb40241fa
add phy_datapath_tb and start datapath simplification
2014-12-19 16:48:22 +01:00
9728a97834
add cont_tb and rewrite cont
2014-12-19 11:15:01 +01:00
9e14b1b051
use new implicit submodules collection and Pipeline
2014-12-19 01:35:18 +01:00
a8e1526407
link_tb: simplify using implicit submodules collect
2014-12-19 01:23:04 +01:00
4f22bc807a
make ctrl/datapath in phy vendor agnostics and simplify imports
2014-12-18 19:45:21 +01:00
9789a78aab
test: clean up imports
2014-12-18 16:45:12 +01:00
9ba9470974
test: create generic PacketStreamer/PacketLogger and use it in link_tb/command_tb
2014-12-18 13:15:39 +01:00
bcc0be10ee
phy: use vivado parameters and fix RX datapath (LSB first)
2014-12-17 23:49:55 +01:00
0f8f89a269
update clock constraints for SATA1 and use sys_clk of 200MHz
...
- data seems stable (mila capture) except when receive the ALIGN primtive from the device, we should maybe disable alignment on the HOST when link is ready...
2014-12-17 19:24:23 +01:00
5a16a5b46d
add very basic PHY stimulator (to see HDD behaviour when we send primitives)
2014-12-17 17:57:37 +01:00
37fe17debe
use Vivado programmer instead of IMPACT
2014-12-17 12:07:11 +01:00
2c0115262b
fix compilation and use new cpu_csr_regions
2014-12-17 12:03:52 +01:00
61bfbbff8a
improve check function
2014-12-17 08:58:02 +01:00
a71fa2f522
link_tb: fix cont regression
2014-12-15 20:00:19 +01:00
fadd21fae2
bist: add count to bist parameters
2014-12-15 19:48:22 +01:00
13d75d3933
move Counter to common and use it in all modules
2014-12-15 19:33:38 +01:00
d88b127abb
create SATACON and use it in bist_tb
2014-12-15 19:13:32 +01:00
ddb9d52270
bist: add ctrl_errors/data_errors and clean up
2014-12-15 19:04:45 +01:00
d193bd3321
hdd: improve debug print
2014-12-15 19:04:07 +01:00
707b43178b
add simple synthetizable BIST
2014-12-15 16:44:12 +01:00
d4cd159c9c
command: fix ValueError msg
2014-12-15 15:34:00 +01:00
0a1403cec5
command: memorize data on RX path before presenting it to the user
2014-12-15 15:31:08 +01:00
d970bfb140
transport: add _get_item and simplify _encode_cmd/_decode_cmd
2014-12-15 13:38:50 +01:00
f226de5ba0
modify addressing (in sectors) and improve hdd model debug
2014-12-15 13:26:53 +01:00
6a783ad291
command: fix TX path with random acknowledge
2014-12-14 21:03:14 +01:00
ddc99febb5
command: address/length in bytes
2014-12-14 20:30:21 +01:00
a284f2a9de
hdd: manage sector_size, limitation to 2048 dwords per dma
2014-12-14 20:30:01 +01:00
8b21e5fd21
hdd: rearrange code (will be easier to understand)
2014-12-14 16:49:35 +01:00
79e82d6ccd
command_tb: add random (still something to fix on TX)
2014-12-14 16:38:38 +01:00
46a39b7d41
rename bfm to hdd and clean up
2014-12-14 16:20:22 +01:00
0959f5b979
command: add fsm for RX Path and manage D2H response in bfm
2014-12-14 15:32:00 +01:00
f01a8934f2
bfm: fix HDD read_dma_cmd, identify_dma_cmd and clean up
2014-12-14 13:14:32 +01:00
623a3883c6
transport: generate sop on RX path
2014-12-14 12:59:02 +01:00
a0cb0c6474
command_tb: add streamer and logger
2014-12-14 12:49:35 +01:00
b6d5e23264
bfm: create basic HDD model
2014-12-14 11:44:12 +01:00
1e68b1a907
remove transport_tb (transport will be tested in command_tb)
2014-12-14 10:57:16 +01:00
b1c71f26bd
use description instead of layout
2014-12-14 10:52:56 +01:00
8f9efde39e
regroup all constants/ definitions in common
2014-12-14 10:45:26 +01:00
11c99f8377
command: wip
2014-12-13 11:33:22 +01:00
eb226c1ade
bfm: dma_skeleton
2014-12-13 01:18:08 +01:00
66ef7950ab
command: code TX part and add command_tb
2014-12-12 22:26:04 +01:00
71f6a16913
transport: remove dma_setup and pio_setup_d2h (not needed our controller)
2014-12-12 18:16:30 +01:00
fe875ea650
remove Layer in module names
2014-12-12 14:35:48 +01:00
b9a9e075fd
transport: merge cmd and data Sink/Source, will be easier
2014-12-12 14:31:00 +01:00
9ae703efbe
transport_tb: add basic test for TX path
2014-12-12 11:22:21 +01:00
7ea46ed7a6
transport: add transport_tb skeleton and fix compilation
2014-12-12 00:56:29 +01:00
Florent Kermarrec