Sebastien Bourdeauducq
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70ffe86356
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New migen.fhdl.std to simplify imports + len->flen
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2013-05-22 17:11:09 +02:00 |
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Sebastien Bourdeauducq
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c82b53f1cd
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bank/description/AutoCSR: add autocsr_exclude
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2013-05-08 20:58:57 +02:00 |
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Sebastien Bourdeauducq
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b9b6df6f29
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bank/eventmanager: refactor, rename EventSourceLevel -> EventSourceProcess, add fully externally controlled event source
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2013-05-08 18:12:26 +02:00 |
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Sebastien Bourdeauducq
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b5b29f6d5d
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bank/description/CSRStorage: set reset property of storage for use in test benches
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2013-05-02 11:49:23 +02:00 |
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Sebastien Bourdeauducq
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dc0304a87b
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bank/description/CSRStorage: support alignment bits
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2013-04-30 18:53:40 +02:00 |
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Sebastien Bourdeauducq
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c4f4143591
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New CSR API
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2013-03-30 17:28:41 +01:00 |
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Sebastien Bourdeauducq
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c4c4765a4e
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bank/csrgen/BankArray: retain name information
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2013-03-25 14:44:15 +01:00 |
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Sebastien Bourdeauducq
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53edc3557e
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bank/description/Register: add get_size
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2013-03-25 14:43:44 +01:00 |
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Sebastien Bourdeauducq
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fc883198ae
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bank/csrgen/BankArray: create banks in sorted order
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2013-03-13 23:07:44 +01:00 |
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Sebastien Bourdeauducq
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52d13959f2
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bank/description: modify reg/mem in-place
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2013-03-13 19:46:34 +01:00 |
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Sebastien Bourdeauducq
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04df076fba
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bank: automatic register naming
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2013-03-12 15:45:24 +01:00 |
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Sebastien Bourdeauducq
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b042757187
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Fix Register name conflict between Pytholite and Bank
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2013-03-10 19:47:21 +01:00 |
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Sebastien Bourdeauducq
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f93695f60e
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bank/eventmanager: use module and autoreg
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2013-03-10 19:29:05 +01:00 |
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Sebastien Bourdeauducq
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cddbc1157d
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bank/description/AutoReg: check that get_memories and get_registers are callable
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2013-03-10 18:11:29 +01:00 |
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Sebastien Bourdeauducq
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68fe4c269c
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bank/csrgen: BankArray
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2013-03-10 00:45:16 +01:00 |
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Sebastien Bourdeauducq
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f1474420df
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bank/description: AutoReg
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2013-03-10 00:43:16 +01:00 |
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Sebastien Bourdeauducq
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d2cbc70190
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bank/description: memprefix
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2013-02-25 23:14:15 +01:00 |
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Sebastien Bourdeauducq
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f9acee4e68
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corelogic -> genlib
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2013-02-22 23:19:37 +01:00 |
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Sebastien Bourdeauducq
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3fae6c8f03
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Do not use super()
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2012-12-18 14:54:33 +01:00 |
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Sebastien Bourdeauducq
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62187aa23d
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migen/bank: do not create interface in default param
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2012-12-06 17:28:28 +01:00 |
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Sebastien Bourdeauducq
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e89c66bf14
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bank/csrgen: interface -> bus
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2012-12-06 17:15:34 +01:00 |
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Sebastien Bourdeauducq
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273d9d285b
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bank/description: define reset value of read signal
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2012-12-05 16:40:44 +01:00 |
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Sebastien Bourdeauducq
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50ed73c937
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New specification for width and signedness
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2012-11-29 21:22:38 +01:00 |
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Sebastien Bourdeauducq
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6eebfce44a
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Refactor Case
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2012-11-29 01:11:15 +01:00 |
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Sebastien Bourdeauducq
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fee22a4631
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Remove Constant
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2012-11-28 23:18:43 +01:00 |
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Sebastien Bourdeauducq
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31cdb02eff
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bank/description: regprefix
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2012-10-15 21:21:59 +02:00 |
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Sebastien Bourdeauducq
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85081793cf
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bank: remove RE signal for field registers
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2012-10-09 19:07:53 +02:00 |
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Sebastien Bourdeauducq
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e410973352
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bank: support for atomic writes
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2012-10-08 18:43:18 +02:00 |
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Sebastien Bourdeauducq
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4164fb4ac9
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bus/csr: configurable data width
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2012-08-26 21:19:34 +02:00 |
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Sebastien Bourdeauducq
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11674242c4
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Use super() instead of calling parent constructors directly
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2012-06-08 18:06:12 +02:00 |
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Sebastien Bourdeauducq
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493b181af1
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bank/description: pad unaligned multi-word registers at the top
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2012-05-21 22:55:23 +02:00 |
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Sebastien Bourdeauducq
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9449bbea0a
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Add LICENSE file
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2012-05-21 19:56:23 +02:00 |
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Sebastien Bourdeauducq
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b9c533be51
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bank/csrgen: allow specifying existing CSR interface
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2012-04-06 14:59:09 +02:00 |
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Sebastien Bourdeauducq
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d8d4e81b6e
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bank/csrgen: fix RE generation
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2012-02-18 18:56:18 +01:00 |
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Sebastien Bourdeauducq
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55a265d967
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bank: add RE signal for registers made of fields
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2012-02-17 23:52:06 +01:00 |
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Sebastien Bourdeauducq
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ef7aea0f31
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bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
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2012-02-15 18:23:31 +01:00 |
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Sebastien Bourdeauducq
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91e279ee04
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bank/csrgen: use new bus API
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2012-02-15 16:42:17 +01:00 |
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Sebastien Bourdeauducq
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0c214b484e
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Use double quotes for all strings
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2012-02-14 13:12:43 +01:00 |
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Sebastien Bourdeauducq
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8a61d9d121
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bus/csr: Rename a->adr d->dat to be consistent with the other buses
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2012-02-13 21:46:39 +01:00 |
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Sebastien Bourdeauducq
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fcd6583cbb
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bank: event manager
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2012-02-06 17:39:32 +01:00 |
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Sebastien Bourdeauducq
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3a2a0c4dd8
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bank: support registers larger than the bus word width
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2012-02-06 16:15:27 +01:00 |
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Sebastien Bourdeauducq
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f3ddfffc47
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bank: refactoring
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2012-02-06 13:55:50 +01:00 |
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Sebastien Bourdeauducq
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1a86f26a66
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bank/csrgen: use enumerate
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2012-02-06 11:18:30 +01:00 |
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Sebastien Bourdeauducq
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107f03fd4b
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Remove uses of declare_signal
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2011-12-18 21:47:48 +01:00 |
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Sebastien Bourdeauducq
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135a2eb868
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bank: support raw registers
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2011-12-18 00:28:04 +01:00 |
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Sebastien Bourdeauducq
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1a845d4553
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32-device, 8-bit CSR bus
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2011-12-17 15:54:49 +01:00 |
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Sebastien Bourdeauducq
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c7b9dfc203
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fhdl: simpler syntax
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2011-12-16 21:30:14 +01:00 |
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Sebastien Bourdeauducq
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39b7190334
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Pay a bit more attention to PEP8
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2011-12-16 16:02:55 +01:00 |
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Sebastien Bourdeauducq
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7582b76406
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bank: fix csrgen address decoder
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2011-12-11 20:15:30 +01:00 |
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Sebastien Bourdeauducq
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4340680704
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Cleanup
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2011-12-05 19:25:32 +01:00 |