Sebastien Bourdeauducq
|
b0b0380ea7
|
flow/network: fix ActorNode default params
|
2012-06-16 22:39:31 +02:00 |
|
Sebastien Bourdeauducq
|
1a576e5c83
|
flow/actor: fix busy signal generation for pipelined actors
|
2012-06-16 22:38:45 +02:00 |
|
Sebastien Bourdeauducq
|
9228e8a96d
|
flow/actor: add single_sink/single_source retrieval methods
|
2012-06-16 22:38:16 +02:00 |
|
Sebastien Bourdeauducq
|
f7cac15b34
|
examples/flow/arithmetic: cleanup
|
2012-06-16 22:37:25 +02:00 |
|
Sebastien Bourdeauducq
|
c1450daa93
|
flow: insert splitters
|
2012-06-16 21:23:42 +02:00 |
|
Sebastien Bourdeauducq
|
5c139511e8
|
examples/flow/arithmetic: simulate
|
2012-06-16 19:23:59 +02:00 |
|
Sebastien Bourdeauducq
|
bde8361e19
|
flow: insert combinators and infer plumbing layout
|
2012-06-16 17:30:54 +02:00 |
|
Sebastien Bourdeauducq
|
da522cd58d
|
Abstract actor graphs
|
2012-06-15 17:52:19 +02:00 |
|
Sebastien Bourdeauducq
|
b14be4c8a3
|
actorlib: ASMI sequential reader
|
2012-06-12 21:04:47 +02:00 |
|
Sebastien Bourdeauducq
|
3a58916a4f
|
examples/dataflow/dma: refactor
|
2012-06-12 19:55:57 +02:00 |
|
Sebastien Bourdeauducq
|
ce9e35b8ef
|
fix SimActor get_fragment
|
2012-06-12 17:52:08 +02:00 |
|
Sebastien Bourdeauducq
|
973c00938d
|
Reorganize examples folder
|
2012-06-12 17:49:50 +02:00 |
|
Sebastien Bourdeauducq
|
8a23451237
|
PureSimulable
|
2012-06-12 17:08:56 +02:00 |
|
Sebastien Bourdeauducq
|
a591510189
|
ASMI simulation models
|
2012-06-12 16:57:00 +02:00 |
|
Sebastien Bourdeauducq
|
b7a84b3750
|
wishbone: base TargetModel class
|
2012-06-10 17:05:10 +02:00 |
|
Sebastien Bourdeauducq
|
ec501e7797
|
bus/wishbone: target model
|
2012-06-10 16:40:33 +02:00 |
|
Sebastien Bourdeauducq
|
f061b25a24
|
bus/wishbone/Tap: remove ack feature
|
2012-06-10 12:46:24 +02:00 |
|
Sebastien Bourdeauducq
|
5964df62db
|
examples/dataflow: only import nx when needed
|
2012-06-08 22:54:04 +02:00 |
|
Sebastien Bourdeauducq
|
009f26bb9d
|
flow/network: refactor graph
|
2012-06-08 22:49:49 +02:00 |
|
Sebastien Bourdeauducq
|
de408b2cba
|
flow/ala: fix typo
|
2012-06-08 22:48:47 +02:00 |
|
Sebastien Bourdeauducq
|
f86170e349
|
actorlib: WB writer simulation OK
|
2012-06-08 21:31:57 +02:00 |
|
Sebastien Bourdeauducq
|
356051e8a8
|
actorlib: WB reader simulation OK
|
2012-06-08 21:31:05 +02:00 |
|
Sebastien Bourdeauducq
|
11674242c4
|
Use super() instead of calling parent constructors directly
|
2012-06-08 18:06:12 +02:00 |
|
Sebastien Bourdeauducq
|
152a7e282e
|
actorlib/sim: use set instead of list to represent active transactions
|
2012-06-08 17:56:52 +02:00 |
|
Sebastien Bourdeauducq
|
910c7806cf
|
actorlib: generator-based generic simulation actor
|
2012-06-08 17:54:03 +02:00 |
|
Sebastien Bourdeauducq
|
b145f9e5e2
|
sim: multiread/multiwrite
|
2012-06-08 17:52:32 +02:00 |
|
Sebastien Bourdeauducq
|
f38ef626de
|
corelogic/record: better repr
|
2012-06-08 17:49:31 +02:00 |
|
Sebastien Bourdeauducq
|
d280723618
|
examples/fir: print Verilog source
|
2012-06-08 14:00:49 +02:00 |
|
Sebastien Bourdeauducq
|
b00e8fa826
|
examples/fir: plot input and output signals
|
2012-06-07 23:20:59 +02:00 |
|
Sebastien Bourdeauducq
|
1c0f636c8d
|
flow: generic parameter passing to Actor from sequential/pipelined
|
2012-06-07 18:24:33 +02:00 |
|
Sebastien Bourdeauducq
|
a1fc86af8f
|
flow: fix actor repr
|
2012-06-07 15:48:35 +02:00 |
|
Sebastien Bourdeauducq
|
680a34465d
|
flow: refactor scheduling models
|
2012-06-07 14:44:43 +02:00 |
|
Sebastien Bourdeauducq
|
493b181af1
|
bank/description: pad unaligned multi-word registers at the top
|
2012-05-21 22:55:23 +02:00 |
|
Sebastien Bourdeauducq
|
9449bbea0a
|
Add LICENSE file
|
2012-05-21 19:56:23 +02:00 |
|
Sebastien Bourdeauducq
|
68cd445662
|
bus/wishbone2asmi: fix cache tag size
|
2012-05-15 15:18:03 +02:00 |
|
Sebastien Bourdeauducq
|
0bea1e2589
|
asmi: dat_wm high to disable data write
|
2012-05-15 14:41:54 +02:00 |
|
Sebastien Bourdeauducq
|
f2c20e4af0
|
bus/asmibus/hub: hack to prevent comb loops
|
2012-04-30 17:11:42 -05:00 |
|
Sebastien Bourdeauducq
|
398ece8fe2
|
fhdl/verilog: add option to display which comb blocks are run
This is a debug hack to help find combinatorial loops in designs.
|
2012-04-30 16:38:40 -05:00 |
|
Sebastien Bourdeauducq
|
0b62e573ae
|
sim: pass extra keyword arguments to Verilog converter
|
2012-04-30 16:38:17 -05:00 |
|
Sebastien Bourdeauducq
|
6a52e44d09
|
fhdl: support len() on signals
|
2012-04-08 18:06:22 +02:00 |
|
Sebastien Bourdeauducq
|
b9c533be51
|
bank/csrgen: allow specifying existing CSR interface
|
2012-04-06 14:59:09 +02:00 |
|
Sebastien Bourdeauducq
|
2a4e49e381
|
fhdl: phase out pads
|
2012-04-02 19:21:43 +02:00 |
|
Sebastien Bourdeauducq
|
1b60c7ff40
|
vpi: delete merged Icarus Verilog patch
|
2012-04-02 19:11:32 +02:00 |
|
Sebastien Bourdeauducq
|
623e8e436a
|
fhdl/verilog: do not attempt to initialize instance and mem output signals
|
2012-04-02 12:59:42 +02:00 |
|
Sebastien Bourdeauducq
|
6e3b25ebb6
|
bus/dfi: reset active low signals to 1
|
2012-04-01 17:43:24 +02:00 |
|
Sebastien Bourdeauducq
|
d3c6b8d16f
|
sim/proxy: support lists
|
2012-04-01 17:19:53 +02:00 |
|
Sebastien Bourdeauducq
|
f3ae22f488
|
fhdl/verilog: initialize internal read-only signals with their reset values
|
2012-04-01 16:39:11 +02:00 |
|
Sebastien Bourdeauducq
|
0dfc215fe8
|
corelogic/roundrobin: handle correctly special case with 1 request source
|
2012-03-31 18:01:40 +02:00 |
|
Sebastien Bourdeauducq
|
94b02aa8ed
|
bus/asmicon: initiator
|
2012-03-30 22:16:31 +02:00 |
|
Sebastien Bourdeauducq
|
bb864c65dc
|
sim: proxy
|
2012-03-30 16:40:26 +02:00 |