Sebastien Bourdeauducq
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bd74d39338
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misoclib -> misoc
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2015-09-23 00:35:02 +08:00 |
Florent Kermarrec
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2ccb5655c9
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global: more pep8
we will have to continue the work... volunteers are welcome :)
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2015-04-13 18:02:26 +02:00 |
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Florent Kermarrec
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f68423f423
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global: pep8 (E302)
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2015-04-13 16:47:22 +02:00 |
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Florent Kermarrec
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d9e09707ae
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global: pep8 (replace tabs with spaces)
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2015-04-13 16:19:55 +02:00 |
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Sebastien Bourdeauducq
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369086a178
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soc: simplify integrated memory parameters
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2015-04-02 00:09:38 +08:00 |
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Florent Kermarrec
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ba8b24df57
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sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
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2015-03-25 16:57:38 +01:00 |
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Florent Kermarrec
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30c2521eb0
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sdram: pass sdram_controller_settings to SDRAMSoC
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2015-03-21 23:12:18 +01:00 |
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Florent Kermarrec
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70469e1f37
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sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
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2015-03-21 21:32:39 +01:00 |
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Florent Kermarrec
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c55199deb9
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misoclib/soc: add _integrated_ to cpu options to avoid confusion
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2015-03-21 20:51:37 +01:00 |
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Florent Kermarrec
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de2f1c31d5
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sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
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2015-03-21 16:56:53 +01:00 |
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Florent Kermarrec
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6e4b7c6cfd
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sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
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2015-03-21 12:55:39 +01:00 |
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Florent Kermarrec
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28d04ec300
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soc: rename with_sdram option to with_main_ram (with_sdram was confusing)
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2015-03-14 00:49:19 +01:00 |
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Florent Kermarrec
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2b9397ff5b
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targets: do not implement sdram if already provided by SoC (allow use of -Ot with_sdram = True)
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2015-03-06 07:56:45 +01:00 |
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Florent Kermarrec
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de698c51e4
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sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
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2015-03-02 11:29:43 +01:00 |
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Florent Kermarrec
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6107b7844a
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test implementation on all targets and fix issues
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2015-02-28 12:04:51 +01:00 |
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Florent Kermarrec
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69e869893d
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remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
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2015-02-28 11:36:15 +01:00 |
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Florent Kermarrec
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2c51adcd68
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misoclib: better organization (create cores categories: cpu, mem, com, ...)
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2015-02-28 09:40:44 +01:00 |
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Florent Kermarrec
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074f576340
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targets: add de0nano (100MHz, integrated bios and SDRAM)
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2015-02-27 19:47:32 +01:00 |