04c64eb1d8
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
2015-06-26 00:20:58 +02:00
ffb6081720
litesata/example_designs: Add missing clock in phy instantiation
2015-06-26 01:20:25 +02:00
a1f7ecc8c5
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
2015-06-10 12:15:59 +02:00
0d1a7b9315
litesata: add mirroring
2015-05-25 14:03:14 +02:00
c3716296ae
litesata/examples_designs: add striping
2015-05-25 14:02:02 +02:00
5daba9af68
litesata: do some cleanup and prepare for RAID
2015-05-23 14:08:56 +02:00
a99aa9c7fd
uart: rename wishbone to bridge
2015-05-09 16:24:28 +02:00
fb5397aa82
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
2015-05-09 16:08:20 +02:00
7bdcbc94cd
litesata: use (some) settings from vivado 2015.1, try to follow all ug476 recommendations to initialize GTX (...), remove automatic reset on top.
...
Works fine @ 3Gbps, still not working @6.0Gbps
2015-05-06 01:33:02 +02:00
3ebe877fd2
use similar names for wishbone bridges and move wishbone drivers to [core]/software
2015-05-02 16:22:30 +02:00
c03c41eb77
litescope: rename host directory to software (to be coherent with others cores)
2015-05-01 20:45:02 +02:00
1281a463d6
litescope/bridge: create a generic wishbone bridge that can be used with different phys (the phy needs to provide a sink/source with 8bits data).
...
- we can now pass a phy to LiteScopeWishboneBridge
- LiteScopeUART2Wishbone is only a specific LiteScopeWishboneBridge
- UART mux is removed since complicated and no longer useful (we can now create easily virtual UART over Ethernet, USB or PCIe) or simply add another UART for debug.
2015-05-01 17:51:18 +02:00
5a930fe7cf
lite* cores: changes permissions (+x) on make.py files and on litepcie init.sh file
2015-04-18 08:51:59 -04:00
1f19e6ae92
litesata: pep8 (E265)
2015-04-13 15:58:58 +02:00
c8bcbfb855
litesata: pep8 (E261, E271)
2015-04-13 15:51:17 +02:00
ea67080462
litesata: pep8 (E225)
2015-04-13 15:44:04 +02:00
a9b42161c0
litesata: pep8 (E222)
2015-04-13 15:29:34 +02:00
77cdb953ad
litesata: pep8 (E401)
2015-04-13 15:27:36 +02:00
8f7751e412
litesata: pep8 (E203)
2015-04-13 15:25:40 +02:00
d0c5bd377a
litesata: pep8 (E302)
2015-04-13 15:12:39 +02:00
808e1fe866
litesata: pep8 (replace tabs with spaces)
2015-04-13 14:59:00 +02:00
ea613cd8ee
litesata: update build core target generation
2015-04-09 00:00:25 +02:00
60124be293
adapt LiteSATA to new SoC
2015-04-01 22:52:19 +02:00
6e2a662dd7
litesata: adapt to new SoC API
2015-04-01 17:37:53 +08:00
9107710f03
litexxx cores: use default baudrate of 115200 for all tests
2015-03-20 12:22:53 +01:00
236ea0f572
liteeth: use bios ip_address in example designs
2015-03-18 18:18:43 +01:00
a266deb58e
LiteXXX cores: fix frequency print in test/test_regs.py
2015-03-17 16:01:25 +01:00
d2cb41bc63
LiteXXX cores: convert port parameter to int if is digit in test/make.py
2015-03-17 15:58:21 +01:00
d8b59c03a2
litesata: avoid hack on kc705 platform with new mibuild toolchain management
2015-03-14 01:08:36 +01:00
52f1c45407
LiteXXX cores: fix test_reg.py
2015-03-04 23:13:14 +01:00
073641faa1
litesata: fix permissions and imports
2015-03-04 00:46:24 +00:00
1d4dc45436
LiteXXX cores: use format in prints
2015-03-03 10:29:28 +01:00
f27e7a4b22
litesata: remove unneeded clock constraint
2015-03-03 10:24:05 +01:00
ff29c86fe1
litesata/kc705: use FMC pin names
2015-03-03 01:02:50 +00:00
649cdeb265
liteXXX cores: use new uart and import FlipFlop/Counter/Timeout from Migen
2015-03-01 16:48:41 +01:00
9e01bf5fdd
litesata: create example design derived from SoC
2015-03-01 11:33:38 +01:00
c21a7956c8
liteXXX cores: remove Identifier duplication
2015-03-01 11:24:58 +01:00
67ca0da1d9
liteXXX cores: share same methodology for on-board tests
2015-03-01 11:21:12 +01:00
7b464b2b1c
litesata: create specialized kc705 platform to avoid duplicating things already in mibuild
2015-03-01 11:03:15 +01:00
b34be816ec
liteXXX cores: remove setup.py and relative paths (we will install misolib of use PYTHON_PATH)
2015-02-28 22:23:48 +01:00
0fd1b9df8d
liteXXX cores: remove redefinition of get_csr_csv
2015-02-28 21:45:05 +01:00
69e869893d
remane GenSoC to SoC (more coherent and we will add support for multiple SoCs with their own Wisbbone/CSR buses in the future)
2015-02-28 11:36:15 +01:00
8e67d6e69f
liteeth: fix example design generation and remove VivadoProgrammer from platfom. (TODO: remove others duplicates)
2015-02-28 11:08:17 +01:00
0dfca49e68
litesata: move file and modify import to misoclib.mem.litesata
2015-02-28 11:03:24 +01:00
Florent Kermarrec
Olof Kindgren
Sebastien Bourdeauducq