Sebastien Bourdeauducq
|
d0676e2dd1
|
migen/fhdl/autofragment: factorize
|
2013-03-09 23:23:24 +01:00 |
|
Sebastien Bourdeauducq
|
d0d2df3c4b
|
fhdl/autofragment: remove legacy functions
|
2013-03-09 23:05:45 +01:00 |
|
Sebastien Bourdeauducq
|
72fb6fd6bd
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fhdl/tools/flat_iteration: generalize
|
2013-03-09 23:03:15 +01:00 |
|
Sebastien Bourdeauducq
|
f53acb92e7
|
fhdl/autofragment: fix submodules
|
2013-03-09 21:15:38 +01:00 |
|
Sebastien Bourdeauducq
|
6da8eb906f
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fhdl/autofragment: empty build_fragment by default
|
2013-03-09 19:10:47 +01:00 |
|
Sebastien Bourdeauducq
|
2b8dc52c13
|
Use common definition for FinalizeError
|
2013-03-09 19:03:13 +01:00 |
|
Sebastien Bourdeauducq
|
b75fb7f97c
|
csr/SRAM: support for writes with memory widths larger than bus words
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2013-03-09 00:50:57 +01:00 |
|
Sebastien Bourdeauducq
|
6fa30053bf
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fhdl/verilog: tristate outputs are always wire
|
2013-03-06 11:30:52 +01:00 |
|
Sebastien Bourdeauducq
|
2059592db2
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software/libcompiler-rt: add ctzsi2
|
2013-03-06 11:10:16 +01:00 |
|
Sebastien Bourdeauducq
|
4d4d6c1f88
|
platforms/m1: add video mixer extension board
|
2013-03-05 23:03:01 +01:00 |
|
Sebastien Bourdeauducq
|
9b4ca987e0
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bus/csr: support memories with larger word width than the bus (read only)
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2013-03-03 19:27:13 +01:00 |
|
Sebastien Bourdeauducq
|
bb5ee8d3bd
|
fhdl/autofragment: bugfixes + add auto_attr
|
2013-03-03 17:53:06 +01:00 |
|
Sebastien Bourdeauducq
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cc8118d35c
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fhdl/autofragment: FModule
|
2013-03-02 23:30:54 +01:00 |
|
Sebastien Bourdeauducq
|
d2491828a4
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csr/SRAM: prefix page register with memory name
|
2013-03-01 12:06:12 +01:00 |
|
Sebastien Bourdeauducq
|
6a412f796e
|
xilinx_ise: add lock cycle to bitgen
|
2013-03-01 11:29:40 +01:00 |
Florent Kermarrec
|
edce543b14
|
adapt to migen changes
|
2013-03-01 01:09:00 +01:00 |
|
Florent Kermarrec
|
80e9db7e61
|
use mibuild for de1 example
|
2013-02-28 23:11:41 +01:00 |
|
Florent Kermarrec
|
58a6acba27
|
use mibuild for de0_nano example
|
2013-02-28 23:02:06 +01:00 |
|
Florent Kermarrec
|
58edd7632c
|
compiles but untested
|
2013-02-28 00:32:42 +01:00 |
|
Sebastien Bourdeauducq
|
c10622f5e2
|
fhdl/verilog: insert reset before listing signals
|
2013-02-27 18:10:04 +01:00 |
|
Florent Kermarrec
|
5accd48a17
|
doc: update
|
2013-02-26 23:45:01 +01:00 |
|
Florent Kermarrec
|
87336128a3
|
sim: update
|
2013-02-26 23:25:10 +01:00 |
|
Florent Kermarrec
|
ae900c9c16
|
examples: use miscope.bridges
|
2013-02-26 23:20:29 +01:00 |
|
Florent Kermarrec
|
5fc89f0c71
|
move spi2csr to briges/spi2csr
|
2013-02-26 23:17:34 +01:00 |
|
Florent Kermarrec
|
f823d06cf1
|
examples: update & simplify
|
2013-02-26 23:14:09 +01:00 |
|
Florent Kermarrec
|
b3ae31ee2f
|
examples/../top: update
|
2013-02-26 23:00:37 +01:00 |
|
Sebastien Bourdeauducq
|
d2cbc70190
|
bank/description: memprefix
|
2013-02-25 23:14:15 +01:00 |
|
Sebastien Bourdeauducq
|
a81781f589
|
fhdl/specials: allow setting memory name
|
2013-02-25 23:14:03 +01:00 |
|
Sebastien Bourdeauducq
|
425de02f42
|
uio/ioo: fix specials
|
2013-02-25 23:13:38 +01:00 |
|
Sebastien Bourdeauducq
|
356416fcdc
|
lm32: update
|
2013-02-24 17:42:28 +01:00 |
|
Sebastien Bourdeauducq
|
70f4c74d46
|
m1crg: advance off-chip DDR clock phase
|
2013-02-24 17:41:56 +01:00 |
|
Sebastien Bourdeauducq
|
5e6505b946
|
bios: print number of memory errors
|
2013-02-24 16:51:03 +01:00 |
|
Sebastien Bourdeauducq
|
b854f1ad32
|
build: support optional MMU
|
2013-02-24 16:28:59 +01:00 |
|
Sebastien Bourdeauducq
|
43343b131f
|
lm32: use submodule
|
2013-02-24 15:57:19 +01:00 |
|
Sebastien Bourdeauducq
|
2b902fdcbd
|
xilinx_ise: import Instance
|
2013-02-24 15:36:56 +01:00 |
|
Sebastien Bourdeauducq
|
55ab01f928
|
fhdl/specials/Instance: _printintbool -> verilog_printexpr
|
2013-02-24 13:08:01 +01:00 |
|
Sebastien Bourdeauducq
|
0caac2246d
|
Use new 'specials' API
|
2013-02-24 13:07:25 +01:00 |
|
Sebastien Bourdeauducq
|
a22ada36d7
|
corelogic -> genlib
|
2013-02-24 12:31:00 +01:00 |
|
Sebastien Bourdeauducq
|
d60ab1d215
|
Use new 'specials' API
|
2013-02-24 12:21:01 +01:00 |
|
Sebastien Bourdeauducq
|
56ae0f0714
|
xilinx_ise: disable SRL extraction on synchronizers
|
2013-02-23 19:43:12 +01:00 |
|
Sebastien Bourdeauducq
|
ef833422c7
|
generic_platform/get_verilog: pass additional args to verilog.convert
|
2013-02-23 19:42:29 +01:00 |
|
Sebastien Bourdeauducq
|
0321513726
|
corelogic -> genlib
|
2013-02-23 19:37:27 +01:00 |
|
Sebastien Bourdeauducq
|
c2d54f481f
|
examples/psync: cleanup
|
2013-02-23 19:14:31 +01:00 |
|
Sebastien Bourdeauducq
|
6abac5907b
|
examples/basic/psync: demonstrate the new features
|
2013-02-23 19:04:11 +01:00 |
|
Sebastien Bourdeauducq
|
a878db1e3c
|
genlib: clock domain crossing elements
|
2013-02-23 19:03:35 +01:00 |
|
Sebastien Bourdeauducq
|
7c4e6c35e5
|
fhdl/verilog: support special lowering and overrides
|
2013-02-23 19:03:16 +01:00 |
|
Sebastien Bourdeauducq
|
3a591c358c
|
examples/fir: better filter
|
2013-02-22 23:19:56 +01:00 |
|
Sebastien Bourdeauducq
|
f9acee4e68
|
corelogic -> genlib
|
2013-02-22 23:19:37 +01:00 |
|
Sebastien Bourdeauducq
|
38664d6e16
|
fhdl: inline synthesis directive support
|
2013-02-22 19:10:02 +01:00 |
|
Sebastien Bourdeauducq
|
587f50cf90
|
doc: new 'specials' API
|
2013-02-22 18:12:42 +01:00 |