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4,960 Commits 42 Branches 14 Tags 30 MiB
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4960 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq c4c22c9ca0 sim: signal writes working 2012-03-05 15:40:21 +01:00
Sebastien Bourdeauducq 9bbec278c6 sim: cleanups 2012-03-04 22:56:56 +01:00
Sebastien Bourdeauducq 2cd71e4b5e sim: signal reads working 2012-03-04 22:33:03 +01:00
Sebastien Bourdeauducq c0b0161ec9 sim: compile VPI module 2012-03-04 21:27:02 +01:00
Sebastien Bourdeauducq 29859acc34 sim: two way IPC working 2012-03-04 19:17:03 +01:00
Sebastien Bourdeauducq 8586daf2dd sim: IPC module (lacks str/int encoding) 2012-03-03 18:55:38 +01:00
Sebastien Bourdeauducq 7f307c54a9 README: clarify license 2012-02-29 20:30:08 +01:00
Sebastien Bourdeauducq 8d4a42887e ddrphy: working on hardware, simulation a bit messed up 2012-02-24 15:44:51 +01:00
Sebastien Bourdeauducq baba267db6 ddrphy: request wrdata_en/rddata_en at the same time as the command 2012-02-24 15:14:58 +01:00
Sebastien Bourdeauducq 17b2588321 ddrphy: reads OK, write data coming out 1/2 cycle too late 2012-02-24 15:05:52 +01:00
Sebastien Bourdeauducq a363eb4a36 ddrphy: partly working 2012-02-24 13:54:10 +01:00
Sebastien Bourdeauducq 3179a27d14 dfii: set data mask 2012-02-23 22:00:51 +01:00
Sebastien Bourdeauducq 92ac69bae3 dfii: new design 2012-02-23 21:21:07 +01:00
Sebastien Bourdeauducq b3ca952a39 s6ddrphy: read path OK in simulation 2012-02-21 17:38:40 +01:00
Sebastien Bourdeauducq b4e041ecf1 s6ddrphy: write path OK in simulation 2012-02-20 23:55:20 +01:00
Sebastien Bourdeauducq ce51653381 s6ddrphy: generate DQ/DQS/DM OE 2012-02-20 16:13:56 +01:00
Sebastien Bourdeauducq cbc3b7fa83 s6ddrphy: DQ/DQS/DM SERDES 2012-02-20 13:45:57 +01:00
Sebastien Bourdeauducq 4c1e18a9b5 s6ddrphy: clock, address and command 2012-02-19 20:49:56 +01:00
Sebastien Bourdeauducq f35cd4a85b Prepare for new DDR PHY 2012-02-19 18:43:42 +01:00
Sebastien Bourdeauducq 1b8cb5b46c bus/dfi: fix multiphase naming 2012-02-19 17:57:04 +01:00
Sebastien Bourdeauducq 1e4e092a55 bios: fix function prototypes 2012-02-18 21:06:35 +01:00
Sebastien Bourdeauducq d8d4e81b6e bank/csrgen: fix RE generation 2012-02-18 18:56:18 +01:00
Sebastien Bourdeauducq 026457a98c Send SDRAM initialization sequence and answer PHY read/write requests. Obstinately refuses to work, unfortunately. 2012-02-18 18:12:14 +01:00
Sebastien Bourdeauducq 55a265d967 bank: add RE signal for registers made of fields 2012-02-17 23:52:06 +01:00
Sebastien Bourdeauducq 92dfbb92dd bus: add interconnect statements function 2012-02-17 23:51:32 +01:00
Sebastien Bourdeauducq f995e8b92e fhdl: check we pass BV to signals 2012-02-17 23:50:54 +01:00
Sebastien Bourdeauducq 5bc840b9c1 DFI injector (untested) 2012-02-17 23:50:10 +01:00
Sebastien Bourdeauducq c38de34a21 bios: DDR initialization skeleton 2012-02-17 18:47:04 +01:00
Sebastien Bourdeauducq e5927e265f bios: add flash target using m1nor 2012-02-17 18:16:29 +01:00
Sebastien Bourdeauducq 48ddbf0c85 Add build Makefile and JTAG load script 2012-02-17 18:09:48 +01:00
Sebastien Bourdeauducq c387ce7ce5 Map DDR PHY controls in CSR 2012-02-17 17:34:59 +01:00
Sebastien Bourdeauducq a1ad30faab fhdl/verilog: properly connect instance inouts 2012-02-17 11:08:41 +01:00
Sebastien Bourdeauducq 5d1dad583b Connect DDR PHY 
Doesn't do much for the moment, just to check synthesis/P&R.
 2012-02-17 11:04:44 +01:00
Sebastien Bourdeauducq cdd58e023b s6ddrphy: use single-ended DQS 2012-02-17 10:53:58 +01:00
Sebastien Bourdeauducq cc5e4ae710 clkfx: remove 2012-02-16 19:30:00 +01:00
Sebastien Bourdeauducq 204452b0d3 m1crg: make clock feedback pin bidirectional 2012-02-16 18:35:44 +01:00
Sebastien Bourdeauducq f36a45edcb lm32: compatibility with the new instance API 2012-02-16 18:35:22 +01:00
Sebastien Bourdeauducq ca7056b07f fhdl: support forwarding of bidirectional signals from instance ports 2012-02-16 18:34:32 +01:00
Sebastien Bourdeauducq 72f9af9d90 Generate all clocks for the DDR PHY 2012-02-16 18:02:37 +01:00
Sebastien Bourdeauducq c08687b9c6 bus/dfi: filter signals by direction 2012-02-15 21:48:05 +01:00
Sebastien Bourdeauducq ef7aea0f31 bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY 2012-02-15 18:23:31 +01:00
Sebastien Bourdeauducq fa9cf3e466 bus: add DFI 2012-02-15 18:09:14 +01:00
Sebastien Bourdeauducq 859c9d8849 Use new bus API 2012-02-15 16:55:13 +01:00
Sebastien Bourdeauducq 91e279ee04 bank/csrgen: use new bus API 2012-02-15 16:42:17 +01:00
Sebastien Bourdeauducq af5230c8ee bus: fix simple interconnect 2012-02-15 16:42:05 +01:00
Sebastien Bourdeauducq 0493212124 bus: simplify and cleanup 
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
 2012-02-15 16:30:16 +01:00
Sebastien Bourdeauducq 1368b666df s6ddrphy: prepare quilt 2012-02-14 15:52:39 +01:00
Sebastien Bourdeauducq b157d84434 README 2012-02-14 15:43:09 +01:00
Sebastien Bourdeauducq 46b1f74e98 bus/asmibus/hub: forward data and tag_call 2012-02-14 14:00:17 +01:00
Sebastien Bourdeauducq aef2e4b5e8 Use double quotes for all strings 2012-02-14 13:15:00 +01:00