Sebastien Bourdeauducq
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382ed013af
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minor cleanups
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2015-04-02 14:40:29 +08:00 |
Florent Kermarrec
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60124be293
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adapt LiteSATA to new SoC
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2015-04-01 22:52:19 +02:00 |
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Sebastien Bourdeauducq
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6e2a662dd7
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litesata: adapt to new SoC API
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2015-04-01 17:37:53 +08:00 |
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Florent Kermarrec
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b313772a0c
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sdram: remove redundant with_l2 parameter (equivalent to l2_size != 0)
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2015-03-29 12:34:40 +02:00 |
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Florent Kermarrec
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a8d91c0c1d
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sdram/module: fix MT8JTF12864, rowbits is 14 and not 16.... (16 was used from the beginning, but it does not fix the runtime issue)
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2015-03-28 16:35:15 +01:00 |
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Florent Kermarrec
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75ee8a5db9
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sdram/phy/simphy: OK with DDR3
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2015-03-28 01:59:55 +01:00 |
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Florent Kermarrec
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51ce7cad6f
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sdram/phy/simphy: expose settings to user and test with DDR/LPDDR/DDR2
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2015-03-28 01:18:35 +01:00 |
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Florent Kermarrec
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a95b3f8f13
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sdram/core/lasmicon: add enabled parameter to refresher (for some simulations we need to disable it)
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2015-03-28 01:17:50 +01:00 |
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Florent Kermarrec
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7fe748e1b0
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sdram/module: clean up tREFI. (use 64ms/8k or 4k)
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2015-03-28 01:09:21 +01:00 |
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Florent Kermarrec
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9137b91e9e
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sdram: remove nbits from modules and databits from GeomSettings
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2015-03-26 23:27:37 +01:00 |
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Florent Kermarrec
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9a9af17aca
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sdram/phy/simphy: remove use of iter
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2015-03-26 23:02:23 +01:00 |
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Florent Kermarrec
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e6de4b1bf9
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sdram/phy: add simphy (software memtest OK in simulation with MT48LC4M16)
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2015-03-26 22:28:32 +01:00 |
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Florent Kermarrec
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257706517e
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software/memtest: remove Mixxeo/M1 hardcoded values in bandwidth computation
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2015-03-26 00:01:42 +01:00 |
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Florent Kermarrec
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ff11cb97a9
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sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True
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2015-03-25 17:22:26 +01:00 |
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Florent Kermarrec
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ba8b24df57
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sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy
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2015-03-25 16:57:38 +01:00 |
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Florent Kermarrec
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7ea9e2ba89
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sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings.
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2015-03-25 16:56:29 +01:00 |
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Florent Kermarrec
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92f81409f2
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sdram/module: fix tREFI on AS4C16M16
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2015-03-22 03:20:02 +01:00 |
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Florent Kermarrec
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30c2521eb0
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sdram: pass sdram_controller_settings to SDRAMSoC
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2015-03-21 23:12:18 +01:00 |
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Florent Kermarrec
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70469e1f37
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sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit)
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2015-03-21 21:32:39 +01:00 |
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Florent Kermarrec
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c60d99583d
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sdram/module: add tREFI uniformization to TODO
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2015-03-21 18:59:16 +01:00 |
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Florent Kermarrec
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0f9b0c6f0f
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sdram/module: add MT47H128M8 DDR2 (used for a customer)
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2015-03-21 18:52:10 +01:00 |
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Florent Kermarrec
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45eb5090db
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sdram/module: add speedgrate note for IS42S16160 and AS4C16M16
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2015-03-21 18:41:59 +01:00 |
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Florent Kermarrec
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a560ba35bd
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sdram/module: add AS4C16M16 for minispartan6
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2015-03-21 18:38:53 +01:00 |
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Florent Kermarrec
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854058a8db
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sdram/module: add description and TODO list
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2015-03-21 17:44:04 +01:00 |
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Florent Kermarrec
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52924ee1f2
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sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705
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2015-03-21 17:25:36 +01:00 |
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Florent Kermarrec
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fd2f8d4bb4
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sdram: define MT46V32M16 and use it on m1/mixxeo
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2015-03-21 17:04:58 +01:00 |
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Florent Kermarrec
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de2f1c31d5
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sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets
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2015-03-21 16:56:53 +01:00 |
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Florent Kermarrec
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6e4b7c6cfd
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sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
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2015-03-21 12:55:39 +01:00 |
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Florent Kermarrec
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9107710f03
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litexxx cores: use default baudrate of 115200 for all tests
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2015-03-20 12:22:53 +01:00 |
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Florent Kermarrec
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236ea0f572
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liteeth: use bios ip_address in example designs
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2015-03-18 18:18:43 +01:00 |
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Florent Kermarrec
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a266deb58e
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LiteXXX cores: fix frequency print in test/test_regs.py
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2015-03-17 16:01:25 +01:00 |
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Florent Kermarrec
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d2cb41bc63
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LiteXXX cores: convert port parameter to int if is digit in test/make.py
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2015-03-17 15:58:21 +01:00 |
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Florent Kermarrec
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d8b59c03a2
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litesata: avoid hack on kc705 platform with new mibuild toolchain management
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2015-03-14 01:08:36 +01:00 |
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Florent Kermarrec
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52f1c45407
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LiteXXX cores: fix test_reg.py
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2015-03-04 23:13:14 +01:00 |
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Sebastien Bourdeauducq
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073641faa1
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litesata: fix permissions and imports
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2015-03-04 00:46:24 +00:00 |
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Florent Kermarrec
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1d4dc45436
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LiteXXX cores: use format in prints
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2015-03-03 10:29:28 +01:00 |
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Florent Kermarrec
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f27e7a4b22
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litesata: remove unneeded clock constraint
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2015-03-03 10:24:05 +01:00 |
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Florent Kermarrec
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905be50451
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sdram: move lasmibus to core, rename crossbar to lasmixbar and move it to core, move dfi to phy
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2015-03-03 09:55:25 +01:00 |
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Florent Kermarrec
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9210272356
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sdram: pass phy_settings to LASMIcon, MiniCON and init_sequence
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2015-03-03 09:23:21 +01:00 |
|
Florent Kermarrec
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2f7206b386
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sdram: revert use of scalar values for DFIInjector
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2015-03-03 09:09:54 +01:00 |
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Florent Kermarrec
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9df60bf98e
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lasmicon: better management of optional bandwidth module (automatically inserted by -Ot with_memtest True)
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2015-03-03 09:02:53 +01:00 |
|
Sebastien Bourdeauducq
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ff29c86fe1
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litesata/kc705: use FMC pin names
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2015-03-03 01:02:50 +00:00 |
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Sebastien Bourdeauducq
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8e48502d03
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spiflash: style
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2015-03-03 00:54:30 +00:00 |
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Florent Kermarrec
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410a162841
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sdram: disable by default bandwidth_measurement on lasmicon
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2015-03-02 19:53:16 +01:00 |
|
Florent Kermarrec
|
473997df26
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cpuif: add CSR_ prefix to CSR base addresses (avoid conflicts between CSR and mems bases)
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2015-03-02 16:52:17 +01:00 |
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Florent Kermarrec
|
8280acd3a7
|
sdram: only keep frontend logic and sdram core declaration in soc/sdram.py, move other logic to sdram/core
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2015-03-02 12:17:49 +01:00 |
|
Florent Kermarrec
|
3465db25a7
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soc/sdram: be more generic in naming
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2015-03-02 11:55:28 +01:00 |
|
Florent Kermarrec
|
97331153e0
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sdram: create core dir and move lasmicon/minicon in it
|
2015-03-02 11:38:22 +01:00 |
|
Florent Kermarrec
|
de698c51e4
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sdram: rename self.phy_settings to self.settings (using phy.settings instead of phy.phy_settings seems cleaner)
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2015-03-02 11:29:43 +01:00 |
|
Florent Kermarrec
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6b24562eea
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sdram: reintroduce dat_ack change (it was a small issue on wishbone writes (sending data 1 clock cycle too late) that was not detected by memtest)
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2015-03-02 10:59:43 +01:00 |