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1,444 Commits 42 Branches 14 Tags 30 MiB
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1444 Commits

Author SHA1 Message Date
Florent Kermarrec 69e9032d49 sofware/memtest: update bandwidth registers 2015-03-25 17:25:39 +01:00
Florent Kermarrec ff11cb97a9 sdram/core/lasmicon: automatically insert bandwidth module when with_memtest is True 2015-03-25 17:22:26 +01:00
Florent Kermarrec ba8b24df57 sdram: pass module as phy parameter, define memtype in modules and only keep phy parameter in register_sdram_phy 2015-03-25 16:57:38 +01:00
Florent Kermarrec 7ea9e2ba89 sdram: use names that are more explicit for bank_a, row_a,...: bankbits, rowbits, .... Add databits to GeomSettings. 2015-03-25 16:56:29 +01:00
Florent Kermarrec 73c2b7ebaa tools: add minimal flterm.py (basic flterm.c clone with kernel loading for now) 
flterm.c is not portable, we need a portable alternative. Once flterm.py will support all flterm features, it will be possible to remove flterm.c.
 2015-03-25 16:47:03 +01:00
Florent Kermarrec 6492ef1efa linker-sdram.ld: sdram mem region is now called main_ram 2015-03-25 16:45:19 +01:00
Florent Kermarrec 20207c9c32 liteusb: give more generic names to modules: FtdiXXX becomes LiteUSBXXX, move PHY outside of core (builds on minispartan6) 2015-03-22 11:11:37 +01:00
Florent Kermarrec c77562f44b liteusb: make oe_n optional on ft2232h phy 2015-03-22 10:56:56 +01:00
Florent Kermarrec ed5746a1fe liteusb: fix imports 2015-03-22 10:56:29 +01:00
Florent Kermarrec a0ee0d8ff6 targets: add minispartan6 (SDRAM working) 2015-03-22 03:29:11 +01:00
Florent Kermarrec 92f81409f2 sdram/module: fix tREFI on AS4C16M16 2015-03-22 03:20:02 +01:00
Florent Kermarrec d33729dda9 targets: pipistrello/ppro, fix stupid mistake 10ex --> 1ex... 2015-03-22 02:33:29 +01:00
Florent Kermarrec cf17f06860 targets: fix CLKIN1_PERIOD on ppro and pipistrello 2015-03-22 00:30:21 +01:00
Florent Kermarrec 30c2521eb0 sdram: pass sdram_controller_settings to SDRAMSoC 2015-03-21 23:12:18 +01:00
Florent Kermarrec 70469e1f37 sdram: simplify the way we pass settings to controller and rename ramcon_type to sdram_controller_type (more explicit) 2015-03-21 21:32:39 +01:00
Florent Kermarrec 9bc71f374a rename sdram mapping to main_ram 2015-03-21 21:01:46 +01:00
Florent Kermarrec c55199deb9 misoclib/soc: add _integrated_ to cpu options to avoid confusion 2015-03-21 20:51:37 +01:00
Florent Kermarrec b75e4b237d software/bios/memtest: add data bus test (0xAAAAAAAA, 0x55555555) on a small portion of the test zone. 
we now need to add another random addressing test to avoid linear access on L2 cache
 2015-03-21 20:29:15 +01:00
Florent Kermarrec c60d99583d sdram/module: add tREFI uniformization to TODO 2015-03-21 18:59:16 +01:00
Florent Kermarrec 0f9b0c6f0f sdram/module: add MT47H128M8 DDR2 (used for a customer) 2015-03-21 18:52:10 +01:00
Florent Kermarrec 45eb5090db sdram/module: add speedgrate note for IS42S16160 and AS4C16M16 2015-03-21 18:41:59 +01:00
Florent Kermarrec a560ba35bd sdram/module: add AS4C16M16 for minispartan6 2015-03-21 18:38:53 +01:00
Florent Kermarrec 711540e15c targets/mlabs_video: rename sdram_module to sdram_modules to reflect that we have 2 modules sharing the same characteristics 2015-03-21 18:10:56 +01:00
Florent Kermarrec 1c0e306176 targets/kc705: rename sdram_module to sdram_modules to reflect that we have 8 modules sharing the same characteristics 2015-03-21 18:07:10 +01:00
Florent Kermarrec 854058a8db sdram/module: add description and TODO list 2015-03-21 17:44:04 +01:00
Florent Kermarrec 52924ee1f2 sdram: define MT46V32M16/MT8JTF12864 and use it on pipistrello/kc705 2015-03-21 17:25:36 +01:00
Florent Kermarrec fd2f8d4bb4 sdram: define MT46V32M16 and use it on m1/mixxeo 2015-03-21 17:04:58 +01:00
Florent Kermarrec de2f1c31d5 sdram: create module.py to define SDRAM modules and use it on de0nano/ppro targets 2015-03-21 16:56:53 +01:00
Florent Kermarrec 6e4b7c6cfd sdram: split sdram_timing in sdram_timing_settings/sdram_controller_settings 
req_queue_size, read_time, write_time settings are not sdram_timing settings but sdram controller settings
 2015-03-21 12:55:39 +01:00
Florent Kermarrec 9107710f03 litexxx cores: use default baudrate of 115200 for all tests 2015-03-20 12:22:53 +01:00
Robert Jordens ec465959d0 pipistrello: add user reset 
apparently needed for flashed bitstream, xiped bios, mor1kx
 2015-03-19 19:01:06 +01:00
Robert Jordens a10875a3b7 pipistrello: fix flash, ddram pin naming 2015-03-19 19:01:06 +01:00
Florent Kermarrec 82fe83a1c4 sdram: raise NotImplementedError if Minicon is used others memories than SDR (not functional for now) 2015-03-19 16:08:03 +01:00
Florent Kermarrec 9f2e5cd7b6 targets/kc705: add external reset 2015-03-19 15:58:04 +01:00
Florent Kermarrec 84b631c929 liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc 2015-03-19 14:52:02 +01:00
Florent Kermarrec 6bdf60567c liteeth/mac/core: fix hw_preamble_crc register generation 2015-03-19 13:03:27 +01:00
Florent Kermarrec 236ea0f572 liteeth: use bios ip_address in example designs 2015-03-18 18:18:43 +01:00
Florent Kermarrec cb4be52922 targets: add Lattice ECP3 versa 2015-03-17 19:09:43 +01:00
Florent Kermarrec 70f1f96fda litescope/drivers: do not build regs when addrmap is None 2015-03-17 16:04:31 +01:00
Florent Kermarrec a266deb58e LiteXXX cores: fix frequency print in test/test_regs.py 2015-03-17 16:01:25 +01:00
Florent Kermarrec d2cb41bc63 LiteXXX cores: convert port parameter to int if is digit in test/make.py 2015-03-17 15:58:21 +01:00
Florent Kermarrec 2327710387 liteeth/phy/gmii : set tx_er to 0 only if it exits 2015-03-17 12:24:06 +01:00
Florent Kermarrec 408d0fd2dd liteeth: use default programmer in make.py 2015-03-17 12:12:21 +01:00
Florent Kermarrec ec6ae75065 liteeth: use CRG from Migen in base example 2015-03-17 12:11:51 +01:00
Florent Kermarrec a874f85854 litescope: use CRG from Migen 2015-03-17 11:52:54 +01:00
Florent Kermarrec b2f32ad124 targets/simple: manual instantiation of CRG (automatic insertion works for BaseSoC but not for MiniSoC since this one define clock_domains) 2015-03-17 01:07:44 +01:00
Florent Kermarrec faf185d58d liteeth: make gmii phy generic 2015-03-16 23:04:37 +01:00
Florent Kermarrec d8b59c03a2 litesata: avoid hack on kc705 platform with new mibuild toolchain management 2015-03-14 01:08:36 +01:00
Florent Kermarrec 28d04ec300 soc: rename with_sdram option to with_main_ram (with_sdram was confusing) 2015-03-14 00:49:19 +01:00
Sebastien Bourdeauducq d09529d483 targets/simple: use mibuild default clock 2015-03-14 00:11:59 +01:00