Florent Kermarrec
|
ce11b30140
|
misoclib: integrate mxcrg.py in mlabs_video target, remove others directory
we should also get rid of mxcrg.v (similar to what is done on papilio or pipstrello)
|
2015-07-24 23:16:45 +02:00 |
|
Florent Kermarrec
|
b75b93df43
|
misoclib/com/uart: replace revered Migen FIFO function with specific _get_uart_fifo function for our use case.
|
2015-07-24 14:05:54 +02:00 |
|
Florent Kermarrec
|
0a115f609e
|
litepcie/frontend/dma: group loop index and count in loop_status register (avoid 2 register reads)
|
2015-07-24 13:52:57 +02:00 |
|
Florent Kermarrec
|
d73d75007e
|
misoclib/com/uart: cleanup and add irq condition parameters
- reintroduce RX/TX split (ease comprehension)
- use FIFO wrapper function from Migen.
- add tx_irq_condition and rx_irq_condition
|
2015-07-24 12:57:42 +02:00 |
|
Florent Kermarrec
|
b1ea3340f3
|
litepcie/frontend/dma: add loop counter (useful to detect missed interrupts)
|
2015-07-22 22:55:11 +02:00 |
|
Florent Kermarrec
|
dfc207aacb
|
litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow)
|
2015-07-22 21:44:53 +02:00 |
|
Florent Kermarrec
|
40740d3ddc
|
litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
We should eventually try to use python package_data or data_file for that.
|
2015-07-22 18:09:04 +02:00 |
Robert Jordens
|
a501d7c52d
|
uart: support async phys
|
2015-07-19 23:37:00 +02:00 |
|
Florent Kermarrec
|
4dca66b23d
|
misoclib/video/dvisampler: add fifo_depth parameter
|
2015-07-13 11:03:33 +02:00 |
|
Florent Kermarrec
|
e6da1d16b2
|
wishbone2lasmi: fix "READ_DATA" state
|
2015-07-09 10:40:32 +02:00 |
|
Florent Kermarrec
|
0545d49294
|
liteeth/core: add with_icmp parameter
|
2015-07-06 21:31:20 +02:00 |
|
Florent Kermarrec
|
e011f9378f
|
use sets for leave_out
|
2015-07-05 22:49:23 +02:00 |
|
Florent Kermarrec
|
c100ef6406
|
liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy)
|
2015-07-05 22:45:53 +02:00 |
|
Florent Kermarrec
|
c1ca928ec2
|
liteeth: small logic optimizations on mac (eases timings on spartan6)
|
2015-07-05 12:31:52 +02:00 |
Sebastien Bourdeauducq
|
31a447154d
|
soc: support constants without value
|
2015-06-28 21:35:37 +02:00 |
|
Florent Kermarrec
|
04c64eb1d8
|
litesata/example_designs: fix core generation (RAID introduced some changes on the PHY)
|
2015-06-26 00:20:58 +02:00 |
Olof Kindgren
|
52e6bf6987
|
litesata/test: Add missing dependency on scrambler in bist_tb
|
2015-06-26 01:20:25 +02:00 |
|
Olof Kindgren
|
ffb6081720
|
litesata/example_designs: Add missing clock in phy instantiation
|
2015-06-26 01:20:25 +02:00 |
|
Florent Kermarrec
|
125432b5b6
|
liteeth/example_designs: use new Keep SynthesisDirective
|
2015-06-23 16:15:28 +02:00 |
|
Florent Kermarrec
|
01c5051866
|
liteeth/software: fix wishbone bridge
|
2015-06-23 01:48:45 +02:00 |
|
Florent Kermarrec
|
369cf4c4d7
|
liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection
|
2015-06-23 01:08:49 +02:00 |
|
Florent Kermarrec
|
5c939b85ef
|
liteeth/core/arp: fix table timer (wait_timer adaptation issue)
|
2015-06-23 00:25:26 +02:00 |
|
Florent Kermarrec
|
a3c0e5c4d9
|
liteeth/core/arp: fix missing MAC address in ARP reply
|
2015-06-22 23:15:00 +02:00 |
|
Florent Kermarrec
|
f44956bfca
|
soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined
|
2015-06-19 08:39:37 +02:00 |
|
Sebastien Bourdeauducq
|
7c2d0fa641
|
indentation
|
2015-06-17 08:32:17 -06:00 |
|
Florent Kermarrec
|
c0bc94ca1c
|
soc/sdram: add capability to share L2 cache in multi-CPU SoCs
|
2015-06-17 15:48:45 +02:00 |
|
Florent Kermarrec
|
3b9f287bab
|
sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon
|
2015-06-17 15:30:30 +02:00 |
|
Florent Kermarrec
|
a1f7ecc8c5
|
litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :)
|
2015-06-10 12:15:59 +02:00 |
|
Florent Kermarrec
|
571ce5791a
|
litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
|
2015-06-10 12:14:48 +02:00 |
|
Florent Kermarrec
|
1bb2580779
|
sdram: use new Migen Converter in Minicon frontend and small cleanup
|
2015-06-02 19:37:08 +02:00 |
|
Florent Kermarrec
|
f96a856c97
|
sdram/phy: fix simphy memory usage
|
2015-06-02 19:33:09 +02:00 |
|
Florent Kermarrec
|
f40140dba5
|
sdram: refactor minicon and fix issues with DDRx memories
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
|
2015-05-29 12:31:56 +02:00 |
|
Sebastien Bourdeauducq
|
d50bb8c55e
|
litesata: more doc fixes
|
2015-05-26 14:13:13 +08:00 |
|
Sebastien Bourdeauducq
|
1e47cfce2b
|
Merge branch 'master' of https://github.com/m-labs/misoc
Conflicts:
misoclib/mem/litesata/doc/source/docs/frontend/index.rst
|
2015-05-26 13:57:26 +08:00 |
|
Sebastien Bourdeauducq
|
a9da892b57
|
litesata: doc fixes
|
2015-05-26 13:54:31 +08:00 |
|
Florent Kermarrec
|
989d8a7c29
|
liteata: fix spelling & mistakes in doc
|
2015-05-26 07:37:09 +02:00 |
|
Florent Kermarrec
|
eb922f6ddc
|
litesata: rework frontend doc and add striping, mirroring
|
2015-05-25 14:04:37 +02:00 |
|
Florent Kermarrec
|
0d1a7b9315
|
litesata: add mirroring
|
2015-05-25 14:03:14 +02:00 |
|
Florent Kermarrec
|
c3716296ae
|
litesata/examples_designs: add striping
|
2015-05-25 14:02:02 +02:00 |
|
Florent Kermarrec
|
0d2db23603
|
litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink)
|
2015-05-25 13:55:15 +02:00 |
|
Florent Kermarrec
|
cb053dc011
|
liteusb/core/packet: fix missing ,
|
2015-05-25 13:53:02 +02:00 |
|
Florent Kermarrec
|
1bb5a05488
|
litesata: add striping module for use of multiple HDDs.
|
2015-05-23 14:12:20 +02:00 |
|
Florent Kermarrec
|
5daba9af68
|
litesata: do some cleanup and prepare for RAID
|
2015-05-23 14:08:56 +02:00 |
|
Florent Kermarrec
|
d9b15e6ef6
|
cores: replace Timeout with new WaitTimer
|
2015-05-12 16:14:38 +02:00 |
|
Florent Kermarrec
|
a99aa9c7fd
|
uart: rename wishbone to bridge
|
2015-05-09 16:24:28 +02:00 |
|
Florent Kermarrec
|
fb5397aa82
|
uart: remove litescope dependency for UARTWishboneBridge and remove frontend
|
2015-05-09 16:08:20 +02:00 |
|
Florent Kermarrec
|
1fd189512f
|
liteusb/frontend/dma: remove +4 to length for CRC (we'll do it in core)
|
2015-05-08 23:10:08 +02:00 |
|
Florent Kermarrec
|
4d902b578c
|
liteusb/phy/ft245: rename "ftdi" clock domain to "usb"
|
2015-05-07 20:03:12 +02:00 |
|
Florent Kermarrec
|
d9111f6a04
|
litesata: fix packets figure in frontend doc
|
2015-05-07 11:06:05 +02:00 |
|
Florent Kermarrec
|
5516a49696
|
litesata: add doc for frontend
|
2015-05-06 03:57:07 +02:00 |