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Author SHA1 Message Date
Florent Kermarrec
d38048baac soc: add initial DMA bus support (optionally provided by CPU(s) for cache coherency). 
When provided, the modules doing DMA shall connect the DMA to the dma_bus to allow the CPU(s) to manage cache coherency
and avoid the manual cache flushes.

This has been tested with VexRiscv SMP and LiteSDCard doing DMA while loading Linux binaries.
 2020-07-22 18:44:37 +02:00
enjoy-digital
2361abb12d
Merge pull request #599 from antmicro/gen-mmcm-pr 
litex-gen: add mmcm core
 2020-07-22 14:52:26 +02:00
Piotr Binkowski
66c5f37133 litex-gen: add mmcm core 2020-07-22 12:34:32 +02:00
Florent Kermarrec
6b72f52c5d boards: keep in sync with litex-boards. 2020-07-22 08:50:38 +02:00
Florent Kermarrec
1f27b7405e soc/integration/add_sdcard: add direct connection to VexRiscv's dmabus for testing. 2020-07-21 19:54:42 +02:00
Florent Kermarrec
408d1a9f5d cpu/vexriscv/system.h: update flush_cpu_dcache. 2020-07-21 19:43:00 +02:00
Florent Kermarrec
47ce15b431 interconnect/wishbone: add minimal UpConverter. 2020-07-21 19:35:14 +02:00
enjoy-digital
9fc488bdf6
Merge pull request #597 from antmicro/jboc/litex-buildenv-add-adapter-fix 
Fix Vivado crash when using 1:1 wishbone.Converter
 2020-07-20 23:11:01 +02:00
enjoy-digital
b92519502a
Merge pull request #595 from betrusted-io/master 
wire up missing register bits.
 2020-07-20 22:47:16 +02:00
enjoy-digital
87d7f6e72e
Merge pull request #598 from sergachev/master 
interconnect/csr_bus: fix paged access warning
 2020-07-20 19:24:21 +02:00
Ilia Sergachev
8656ea9b67 interconnect/csr_bus: fix paged access warning 2020-07-20 18:23:09 +02:00
Jędrzej Boczar
07bc589c41 fix/Vivado: don't instantiate wishbone.Converter in add_adapter when not needed 
Fixes an issue with Vivado which crashes with SIGSEGV when building litex-buildenv at:
cc003bef3a
and litex bumped to 4a18b828bc,
with options:
    CPU=mor1kx; CPU_VARIANT=linux; PLATFORM=arty; FIRMWARE=linux; TARGET=net
The only difference in Verilog is that we avoid creating new Interface and doing
`new_interface.connect(interface)`, so this shouldn't make any difference, but
this somehow generates the error in Vivado (tested on v2018.3 and v2019.2).
 2020-07-20 15:26:21 +02:00
Florent Kermarrec
4a18b828bc software/liblitesdcard/spisdcard: remove optimization on receive_block (not working on all configs) and increase max clk_freq to 20MHz. 2020-07-20 13:48:49 +02:00
Florent Kermarrec
100aa5a4ca soc/cores/spi/SPIMaster: rewrite/simplify. 
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
 2020-07-20 10:44:18 +02:00
bunnie
53a567daef wire up missing register bits. 
Not sure how they went missing...but just noticed them.
 2020-07-19 03:00:25 +08:00
Florent Kermarrec
63c19ff45f liblitesdcard/spisdcard: update comments. 2020-07-17 15:39:39 +02:00
Florent Kermarrec
1f34f6ef00 soc/cores/spi: make sure done and miso are synchronous. 2020-07-17 15:38:52 +02:00
Florent Kermarrec
754f140a9d spisdcard: revert to 8-bit SPI, optimize spisdcardreceive_block and reduce clk to 12.5MHz for now. 2020-07-17 11:58:26 +02:00
Florent Kermarrec
8143f1a08b soc/cores/spi: make sure miso is stable during xfer. 2020-07-17 11:56:27 +02:00
Florent Kermarrec
ac35e158c1 bios/boot: add bootargs support on netboot/sdcardboot to optionally specify r1/r2/r3/addr. 
For example:
{
	"Image":  "0x40000000",
	"bootargs": {
		"r1":  "0x12345678",
	}
}

will copy Image to 0x40000000 and set r1 to 0x12345678.

By default, r1,r2,r3 are set to 0 and addr is the address if the last loaded image, so:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
}

is equivalent to:

{
	"Image":         "0x40000000",
	"rootfs.cpio":   "0x40800000",
	"rv32.dtb":      "0x41000000",
	"emulator.bin":  "0x41100000",
	"bootargs": {
		"r1":   "0x00000000",
		"r2":   "0x00000000",
		"r3":   "0x00000000",
		"addr": "0x00000000",
	}
}
 2020-07-16 18:12:11 +02:00
enjoy-digital
ee4b1d81a7
Merge pull request #594 from antmicro/jboc/axi-lite 
Add AXILiteDownConverter
 2020-07-16 17:56:33 +02:00
Jędrzej Boczar
229da572ff soc/interconnect/axi: propagate response errors in AXILiteDownConverter 2020-07-16 17:16:35 +02:00
Jędrzej Boczar
93bcc94b53 soc/interconnect/axi: implement AXILite down-converter 2020-07-16 17:02:49 +02:00
enjoy-digital
21c48eed76
Merge pull request #593 from antmicro/jboc/axi-lite 
Add AXILite components: AXILiteSRAM and AXILite2CSR
 2020-07-16 11:56:57 +02:00
Jędrzej Boczar
0be607dad9 soc/integration: revert bus argument for add_ram/add_rom 2020-07-16 10:26:12 +02:00
Jędrzej Boczar
2700ec3ce5 soc/integration: use AXILiteConverter (dummy implementation) in add_adapter() 2020-07-15 15:59:16 +02:00
Jędrzej Boczar
f3072d4984 soc/interconnect/axi: add connect methods for convenience 2020-07-15 15:48:40 +02:00
Jędrzej Boczar
78a631f392 test/axi: add AXILite2CSR and AXILiteSRAM tests 2020-07-15 12:40:39 +02:00
enjoy-digital
e12bebb8e1
Merge pull request #592 from antmicro/fix-symbiflow-makefile 
symbiflow: changed toolchain command names in Makefile
 2020-07-15 12:08:21 +02:00
Jędrzej Boczar
a5be2cd257 soc/interconnect/axi: improve SRAM/CSR access speed 2020-07-15 11:44:14 +02:00
Alessandro Comodi
3f7568de09 symbiflow: changed toolchain command names in Makefile 
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
 2020-07-15 11:31:06 +02:00
Jędrzej Boczar
d8a242d86f soc/interconnect: add AXILite SRAM 2020-07-15 10:58:34 +02:00
Jędrzej Boczar
b692b2a3f1 soc/interconnect: add AXILite2CSR bridge 2020-07-15 10:36:34 +02:00
Jędrzej Boczar
35149c4e80 soc/integration: update add_adapter to convert between AXILite/Wishbone 2020-07-14 16:31:46 +02:00
Florent Kermarrec
6671eb6218 build/lattice/trellis: set default spimode to None (--spimode not passed to ecppack) as default instead of fast-read. 
Using fast-read as default prevent loading the .bit via JTAG (see #589).
 2020-07-13 11:55:03 +02:00
Florent Kermarrec
ae3c78f6d1 build/lattice/trellis: fix spimode typo. 2020-07-11 21:30:19 +02:00
enjoy-digital
7c381dadc2
Merge pull request #588 from oskirby/trellis-spimode 
trellis: Add option to select SPI mode.
 2020-07-11 21:26:55 +02:00
Owen Kirby
0aec5b0f8c trellis: Add option to select SPI mode. 
This allows a significant speedup when booting large bitstreams on ECP5
boards that support dual or quad SPI operation.
 2020-07-11 11:48:10 -07:00
enjoy-digital
e76464167b
Merge pull request #587 from antmicro/mor1x_ror_instruction 
mor1kx: Do not generate the ror instruction
 2020-07-10 11:21:13 +02:00
Florent Kermarrec
468db3cf08 integration/soc/sdcard: add mode parameter to enable read only, write only or read+write modes. 2020-07-10 11:18:22 +02:00
Mateusz Holenko
b8d900862c mor1kx: Do not generate the ror instruction 
The mor1kx core does not support `l.ror` instruction
by default, but gcc/clang flags allowed the
compiler to generate it.
 2020-07-10 11:07:12 +02:00
Florent Kermarrec
b7e4507686 core/cpu/CPUNone: set endianness to little. 2020-07-10 10:42:00 +02:00
Tim Ansell
0eb1f88bb4
Merge pull request #585 from FFY00/more-gcc 
cpu: add a few missing GCC toolchains
 2020-07-09 09:34:22 -07:00
Filipe Laíns
235e8cf62b
cpu: add a few missing GCC toolchains 
This names are used by Arch Linux for eg.

Signed-off-by: Filipe Laíns <lains@archlinux.org>
 2020-07-09 15:58:33 +01:00
Florent Kermarrec
5ebdfd9307 liblitesdcard/sdcard: clamp divider value. 2020-07-09 13:09:36 +02:00
enjoy-digital
23085cffea
Merge pull request #584 from ozbenh/memtest 
Memtest/memspeed improvements
 2020-07-09 12:54:42 +02:00
Florent Kermarrec
5c332e4b58 cores/dma: add stream.last support on WishboneDMAReader. 2020-07-09 12:18:09 +02:00
Benjamin Herrenschmidt
83d24d087d memspeed: Write a fixed value 
Otherwise we have at least an extra addition in the loop
which squews the result compared to the read loop.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2020-07-08 17:13:37 +10:00
Florent Kermarrec
146ead4c4c buid/io/InferedSDRIO/InferedSDRTristate: avoid unnecessary clk_domain/limitation. 
Just create a local clk_domain from clk signal.
 2020-07-08 08:33:52 +02:00
Florent Kermarrec
b54b3b3362 interconnect/avalon: minor cleanup, remove max on SyncFIFO depth. 2020-07-08 07:53:42 +02:00