Commit Graph

143 Commits

Author SHA1 Message Date
Florent Kermarrec d45991d6eb fix README 2015-01-23 01:07:51 +01:00
Florent Kermarrec ea48f44b90 add LiteScopeLA example 2015-01-23 00:46:24 +01:00
Florent Kermarrec 5c40ff02cb add LiteScopeIO example 2015-01-23 00:15:42 +01:00
Florent Kermarrec f35f93a7c5 start refactoring and change name to LiteScope 2015-01-23 00:02:53 +01:00
Florent Kermarrec 609f8f9abb revert submodules/specials/clock_domains syntax 2015-01-22 14:00:50 +01:00
Florent Kermarrec fadac0cf83 drivers: fix mask generation when using cond 2015-01-16 23:50:33 +01:00
Florent Kermarrec 8f14f67ea6 simplify UART2Wishbone and add timeout 2015-01-14 18:10:37 +01:00
Florent Kermarrec 54597f1bfc use new submodules/specials/clock_domains automatic collection 2015-01-14 13:55:18 +01:00
Florent Kermarrec 834e9b99be host/drivers: add possibility to pass cond dict to ease trigger pattern generation 2014-12-23 20:53:05 +01:00
Florent Kermarrec 8c5c32751e add input pipe stage option 2014-10-28 20:53:26 +01:00
Florent Kermarrec d860813dec use new direct access on endpoints 2014-10-16 17:57:30 +02:00
Florent Kermarrec 9649b1497c uart2wishbone: fix missing payload.d 2014-10-16 09:37:43 +02:00
Florent Kermarrec 2319ee0ab7 uart2wishbone: always use payload.d and not .d 2014-10-15 12:13:22 +02:00
Florent Kermarrec 027ddc65ca fill __init__.py to simplify imports 2014-10-10 17:24:36 +02:00
Florent Kermarrec bf95ea6c1c mila: simplify usage 2014-10-10 16:17:12 +02:00
Florent Kermarrec d0c9838dca uart2wishbone: share UARTRX and UARTTX with MiSoC 2014-10-10 15:15:58 +02:00
Florent Kermarrec ba30a01830 mila: fixes when used without RLE 2014-10-06 12:30:06 +02:00
Florent Kermarrec f72f11f7b4 mila: add clk_domain support
an AsyncFIFO is inserted when clk_domain is not "sys" to enable capture from another clock domain.
sys_clk frequency need to be greater than clk_domain clock.

future possible improvement: automatic insertion of a converter when clk_domain frequency is
greater than sys_clk.
2014-10-06 12:07:20 +02:00
Florent Kermarrec 7043e6a5f3 mila: simplify export 2014-10-01 10:06:59 +02:00
Florent Kermarrec 111f527647 do some clean up 2014-09-24 22:26:33 +02:00
Florent Kermarrec 2fb418a373 use new MiSoC UART with phase accumulators
this will allow to speed up MiLa reads
2014-09-24 21:56:15 +02:00
Florent Kermarrec 452a4a76f3 use verilog namespace to export mila configuration 2014-08-03 17:09:01 +02:00
Florent Kermarrec 6ffed70b59 uart2wishbone: disconnect rx line from shared pads when bridge is selected
(avoid CPU crash when we communicate with the bridge)
2014-08-03 13:15:56 +02:00
Florent Kermarrec f4e6cebab2 clean up 2014-08-03 11:44:27 +02:00
Florent Kermarrec cd51e78f54 storage: use SyncFIFOBuffered to implement fifo in block ram 2014-08-02 19:12:03 +02:00
Florent Kermarrec 47a85cc1ad use new MiSoC fifo (no flush signal) 2014-08-01 10:36:15 +02:00
Florent Kermarrec a0df5baa55 host: add support for various csr_data width (8 & 32 tested, but should work with others) 2014-06-26 13:22:21 +02:00
Florent Kermarrec 0f9bc5ad6e fix bit inversion on CSV/PY exports 2014-06-21 19:06:47 +02:00
Florent Kermarrec 074a12b444 create dump class and specific export functions, add python dictionnary export 2014-06-19 13:24:47 +02:00
Florent Kermarrec a737358919 host: split read/export and add csv export 2014-06-17 11:25:10 +02:00
Florent Kermarrec 8719206a3a uart2wishbone: add default baudrate 2014-06-05 15:13:20 +02:00
Florent Kermarrec b94cba2d4b mila: add input pipe to ease timing 2014-05-24 09:23:16 +02:00
Florent Kermarrec 31e142fd88 drivers: clean up / fixes 2014-05-22 18:33:28 +02:00
Florent Kermarrec 9a059336bf storage: simplify run length encoder... 2014-05-22 18:13:27 +02:00
Florent Kermarrec 0bc1cd6f77 fix uart selection when opening wishbone 2014-05-22 16:11:32 +02:00
Florent Kermarrec 1a07116ab1 change export format and simplify usage 2014-05-20 13:16:24 +02:00
Florent Kermarrec ba0382ad92 move some functions in drivers and export layout in csv 2014-05-20 11:36:10 +02:00
Florent Kermarrec 2312127c1f simplify and clean up 2014-05-20 09:56:35 +02:00
Florent Kermarrec 6f47a928b1 storage: simplify recorder... 2014-05-13 21:30:32 +02:00
Florent Kermarrec c7e100f93b sim: fix tb_trigger_csr 2014-05-13 17:45:15 +02:00
Florent Kermarrec 4c77c971f2 README: update and point to misoc-de0nano examples 2014-04-21 00:31:02 +02:00
Florent Kermarrec 171224329e drivers: add genericity & prog_range_detector, prog_edge_detector methods 2014-04-21 00:17:23 +02:00
Florent Kermarrec 7a489b3135 refactor code 2014-04-20 23:53:33 +02:00
Florent Kermarrec b766af0d99 uart2csr: add pads parameter 2013-09-25 15:07:23 +02:00
Florent Kermarrec 69009c8405 mila: test rle 2013-09-22 21:23:51 +02:00
Florent Kermarrec a880862628 mila: symplify usage 2013-09-22 13:28:12 +02:00
Florent Kermarrec 27f26dac03 use custom Records instead of Sink/Source (semms easier, but will be reverted if not) 2013-09-22 13:14:11 +02:00
Florent Kermarrec 39f1f2146f storage: add run length encoder 2013-09-22 12:35:46 +02:00
Florent Kermarrec 4fd6619171 trigger: add range_detector / edge_detector 2013-09-22 12:15:11 +02:00
Florent Kermarrec 980a83a74c move trigger/recorder 2013-09-22 11:46:02 +02:00