e78d950a31
soc/interconnect/axi: add AXILite -> AXI converter
2020-07-30 13:50:34 +02:00
879e6ffe73
soc/interconnect/axi: add basic AXI Lite up-converter
2020-07-24 13:47:18 +02:00
32160e615f
soc/interconnect/axi: separate AXI Lite converter channels
2020-07-24 09:25:57 +02:00
a9d8b81385
test/axi: move all AXI Lite tests to separate file
2020-07-22 17:16:33 +02:00
8ae501c391
test/axi: add crossbar stress tests
2020-07-22 17:16:33 +02:00
32d9e212c5
soc/interconnect/axi: improve Timeout module and test it with shared interconnect
2020-07-22 17:16:33 +02:00
2cab7fbf0f
test/axi: add shared AXI Lite interconnect tests
2020-07-22 17:16:33 +02:00
3a08b21d44
soc/interconnect/axi: implement AXI Lite decoder
2020-07-22 17:16:33 +02:00
214cfdcaeb
soc/interconnect/axi: lock AXILiteArbiter until all requests have been responded to
2020-07-22 17:16:33 +02:00
baf23c9c9b
test/test_axi: add AXI Lite interconnect arbiter tests
2020-07-22 17:16:29 +02:00
f47ccdae99
soc/interconnect/axi: point-to-point interconnect and timeout module with tests
2020-07-22 17:16:12 +02:00
47ce15b431
interconnect/wishbone: add minimal UpConverter.
2020-07-21 19:35:14 +02:00
100aa5a4ca
soc/cores/spi/SPIMaster: rewrite/simplify.
...
- Make sure MOSI is latched on start, MISO is stable during Xfer (last value).
- Allow clk_divider down to 2.
- improve test errors reporting with hex() on AssertEqual.
2020-07-20 10:44:18 +02:00
93bcc94b53
soc/interconnect/axi: implement AXILite down-converter
2020-07-16 17:02:49 +02:00
78a631f392
test/axi: add AXILite2CSR and AXILiteSRAM tests
2020-07-15 12:40:39 +02:00
5d202ddb97
test: update.
2020-06-02 13:51:48 +02:00
80ec5eca76
boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform.
2020-06-02 12:18:12 +02:00
7434376c07
test/test_targets: add arty_symbiflow
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Signed-off-by: Mariusz Glebocki <mglebocki@antmicro.com>
2020-06-01 21:41:56 +02:00
3d06dc028c
test/test_targets: update build_test.
2020-05-22 08:42:02 +02:00
ce49990084
Extend I2S capabilities
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This commit:
* adds the support for I2S standard mode,
* extends I2S left justified mode,
* allows to configure sample size for tx/rx in 1-32 bits range,
* implements I2S master mode,
* allows to concatenate channels or used the padded mode.
This required to rework the FSM.
2020-05-20 14:31:51 +02:00
6f8f0d2346
litex_setup: add litehyperbus and remove hyperbus core/test.
2020-05-19 15:49:25 +02:00
9f941138d2
test/test_targets: workaround to fix travis.
2020-05-13 11:04:40 +02:00
98d1b45157
platforms/targets: fix CI.
2020-05-05 15:55:09 +02:00
0b3c4b50fa
soc/cores/spi: add optional aligned mode.
...
In aligned mode, MOSI and MISO bits are located on the LSBs and first transmitted MOSI bit is length - 1 bit.
2020-04-22 13:15:51 +02:00
4fe31f0760
cores: add External Memory Interface (EMIF) Wishbone bridge.
...
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
2020-04-12 16:34:33 +02:00
383fcd36d6
soc/cores/clock: add CycloneVPLL.
2020-04-07 17:24:12 +02:00
0f17547c5b
soc/cores/clock: add initial AlteraClocking/CycloneIV support.
2020-04-07 16:59:53 +02:00
c154d8d2fc
test/test_targets: remove versa_ecp3.
2020-03-25 08:47:43 +01:00
f03d862c06
targets: switch to add_ethernet method instead of EthernetSoC.
2020-03-20 23:46:15 +01:00
eb9f54b2bc
test: add initial (minimal) test for clock abstraction modules.
...
Also fix divclk_divide_range on S6DCM.
2020-03-13 12:38:23 +01:00
54fb3a61cd
test/test_targets: use uart-name=stub.
2020-02-29 11:07:10 +01:00
1d70ef6958
soc/cores/spi_opi: cleanup, rename to S7SPIOPI (since 7-Series specific for now)
2020-02-06 17:58:01 +01:00
f58e8188b7
soc/cores/i2s: cleanup pass, rename to S7I2SSlave (since 7-Series specific for now), rename fifodepth to fifo_depth for consistency with others cores.
2020-02-06 17:00:04 +01:00
f3f9808d1f
interconnect/stream: add PipeValid and PipeWait to cut timing paths.
2020-01-29 18:27:29 +01:00
7b92a17c6e
test/test_targets: limit max_sdram_size to 1GB
2020-01-17 13:24:45 +01:00
68e225fb45
test/test_targets: update
2020-01-15 13:09:03 +01:00
04017519c8
soc/interconnect/axi: add Wishbone2AXILite
2019-11-20 12:32:22 +01:00
4b073a440a
test/test_axi: cosmetic
2019-11-20 11:22:39 +01:00
6059712794
test/test_packet: add randomness on ready output, fix corner-cases on Packetizer/Depacketizer
2019-11-16 14:39:18 +01:00
9642893371
test/test_packet: add randomness on valid input, fix corner-cases on Packetizer
2019-11-16 08:49:04 +01:00
33c4d961b5
test/test_packet: add 32/64/128-bit loopback tests (passing :))
2019-11-15 11:37:52 +01:00
824faf9722
test/test_packet: prepare for testing dw > 8-bit
2019-11-15 11:32:42 +01:00
442e23d7fd
test: add initial test_packet
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Use a header with 8,16,32,64,128-bit fields and test a Packetizer/Depacketizer loopback with random field values, random packet data & length.
2019-11-15 10:29:50 +01:00
650df0ebc2
test/test_targets: skip Minerva test on Travis-CI, remove commented tests
2019-10-28 11:00:08 +01:00
41ad08e8ef
soc/cores/icap: simplify ICAPBitstream (untested)
2019-10-01 21:30:14 +02:00
63a813af9c
soc_core: fix cpu_type=None case and add test for it
2019-09-30 08:26:38 +02:00
241c3c642b
test/test_targets: update cpu-type to mor1kx
2019-09-29 17:12:15 +02:00
8c080e5fb6
soc/interconnect/csr: add initial field support
2019-09-13 20:01:31 +02:00
41fe7cae0b
core/spi: add minimal SPISlave
2019-08-29 09:46:20 +02:00
4990bf33c0
soc/core: simplify/cleanup HyperRAM core
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- rename core to hyperbus.
- change layout (cs_n with variable length instead of cs0_n, cs1_n).
- use DifferentialOutput when differential clock is used.
- add test (python3 -m unittest test.test_hyperbus).
Usage example:
from litex.soc.cores.hyperbus import HyperRAM
self.submodules.hyperram = HyperRAM(platform.request("hyperram"))
self.add_wb_slave(mem_decoder(self.mem_map["hyperram"]), self.hyperram.bus)
self.add_memory_region("hyperram", self.mem_map["hyperram"], 8*1024*1024)
2019-08-16 14:04:58 +02:00
Jędrzej Boczar
Florent Kermarrec
Mariusz Glebocki
Pawel Sagan