Commit Graph

4104 Commits

Author SHA1 Message Date
Florent Kermarrec efce434aa9 bios/sdram: use ddrphy_half_sys8x_taps_read() for KUSDDRPHY 2018-12-17 11:43:21 +01:00
Tim Ansell 0ade06c0f0
Merge pull request #138 from mithro/mainram-hack
Hack to fix #136.
2018-12-16 14:42:36 -08:00
Tim 'mithro' Ansell 22d454efcd Hack to fix #136. 2018-12-16 14:40:10 -08:00
Tim Ansell fa6fef1e15
Merge pull request #135 from mithro/icestorm-ice40up5k
Add uwg30 package and up3k part.
2018-12-16 14:04:19 -08:00
Tim 'mithro' Ansell 9481781d1c Add uwg30 package and up3k part. 2018-12-16 14:03:29 -08:00
Florent Kermarrec e9f1049200 soc/cores/cpu/vexriscv: add add_debug method for debug variants 2018-12-12 10:01:49 +01:00
Florent Kermarrec 35155e5172 soc/cores/cpu/vexriscv: add support for the new variants. 2018-12-12 09:39:30 +01:00
Florent Kermarrec 2ace45e6f8 soc/cores/cpu/vexriscv: update submodule 2018-12-12 09:38:53 +01:00
Florent Kermarrec 6d6c2b4c45 soc/cores/cpu/lm32: add submodule/rtl to include path (needed for lm32_include.v) 2018-12-12 09:38:10 +01:00
Florent Kermarrec 584fd51c01 build/sim/verilator: add support for plaform.sources, some cleanup 2018-12-12 09:37:24 +01:00
Florent Kermarrec c9915f89ce build/microsemi/libero_soc: fix typos 2018-12-12 09:34:43 +01:00
Florent Kermarrec 99578bc68c gen/sim/core: add args support on Display 2018-12-09 09:46:10 +01:00
Florent Kermarrec fa260f5b42 gen/fhdl: add simulation Display, Finish support.
In some simulation cases, it's easier to add debug traces directly in the code
than in the verilog/Migen testbench. This adds support for verilog $display in
Migen code.

Being able to terminate a simulation from the code is also useful, this also
add support for verilog $finish.
2018-12-09 09:45:17 +01:00
Florent Kermarrec 92a6169d2a build/sim: add coverage parameter to enable code coverage 2018-12-09 08:10:50 +01:00
Florent Kermarrec 0c687bc29e soc/interconnect/stream: add support for buffered async fifo 2018-12-08 01:24:08 +01:00
Florent Kermarrec bf3b4eec34 gen: integrate migen changes 2018-12-04 21:06:51 +01:00
Florent Kermarrec 96527b5a3a soc/interconnect/stream/gearbox: remove bit reversing by changing words order 2018-11-30 23:12:30 +01:00
Florent Kermarrec 1c8c2426b9 Merge branch 'master' of http://github.com/enjoy-digital/litex 2018-11-27 17:45:07 +01:00
Florent Kermarrec 8887fc24c4 build/xilinx/vivado: disable xpm by default (can be enabled by passing enable_xpm=True to build).
Old version of Vivado don't have XPM support and enable it break the build.
Enabling XPM is only useful in some cases, we can do it manually.
2018-11-27 17:42:39 +01:00
enjoy-digital cc4ba65659
Merge pull request #130 from jfng/master
litex_sim: add --trace argument
2018-11-27 17:35:03 +01:00
Florent Kermarrec ec46beeb47 targets/ulx3s, versa_ecp5: use ECP5PLL 2018-11-27 17:31:53 +01:00
Jean-François Nguyen 71398e0155 litex_sim: add --trace argument 2018-11-27 17:26:32 +01:00
Florent Kermarrec 18048eb454 cores/clock: test and fix ECP5PLL, phase still not implemented. 2018-11-27 17:24:22 +01:00
Florent Kermarrec 20dd95c541 boards/platforms/ulx3s: add gpios 0-3 2018-11-27 14:15:35 +01:00
Florent Kermarrec 909cff1940 bios/sdram: flush l2 cache only when present 2018-11-26 18:37:45 +01:00
Florent Kermarrec 2ad83778bf bios: allow testing main_ram at init when using an external controller 2018-11-26 15:21:00 +01:00
Florent Kermarrec cdfe0454bb build/microsemi/libero_soc: small cleanup 2018-11-26 11:35:06 +01:00
enjoy-digital 4592e3235b
Merge pull request #128 from mithro/small-fix
Two small fixes
2018-11-26 09:48:10 +01:00
Tim 'mithro' Ansell 4f565c5179 stream.Endpoint: Pass extra arguments to superclass. 2018-11-25 12:57:11 -08:00
Tim 'mithro' Ansell 3b9e4c4df6 wishbone.SRAM: Support non-32bit wishbone widths. 2018-11-25 12:56:37 -08:00
Florent Kermarrec 515c06219a cores/clock: add ECP5PLL 2018-11-24 00:47:38 +01:00
Florent Kermarrec 7623b5dd96 soc/interconnect/stream/gearbox: inverse bit order 2018-11-23 18:34:24 +01:00
Florent Kermarrec d32e393033 soc/cores/spi_flash: add missing endianness parameter 2018-11-23 18:33:53 +01:00
Florent Kermarrec c954943e02 platforms/avalanche: add IOStandard on ddram pins 2018-11-23 12:47:45 +01:00
Florent Kermarrec 09a1cda943 build/microsemi/libero_soc: associate timings constraints with synthesis/place&route/timing verification 2018-11-23 09:30:13 +01:00
Florent Kermarrec a98e1ad689 build/microsemi/libero_soc: add additional_timing_constraints 2018-11-23 09:04:42 +01:00
Florent Kermarrec b166882308 build/microsemi/libero_soc: use die/package/speed from platform.device and add tcl_name helper 2018-11-23 08:26:31 +01:00
Florent Kermarrec 9df75d7d63 platforms/avalanche: add package/speed to platform.device 2018-11-23 08:24:29 +01:00
Florent Kermarrec 953b1f70df build/microsemi/libero_soc: remove previous impl directory if exists 2018-11-23 08:11:57 +01:00
Florent Kermarrec 18d513a146 build/microsemi/libero_soc: give better names to pdc files: io/fp 2018-11-23 08:03:55 +01:00
Florent Kermarrec 4f092dbe35 build/microsemi/libero_soc: add additional_constraints 2018-11-22 18:40:19 +01:00
Florent Kermarrec 206c9a4697 platforms/avalanche: fix ddram dq7 2018-11-22 18:13:33 +01:00
Florent Kermarrec f003407776 build/microsemi/libero_soc: add {} around port name. 2018-11-22 17:37:03 +01:00
Florent Kermarrec beeca856e5 utils/litex_read_verilog: fix generated indent on instance 2018-11-22 17:33:46 +01:00
Florent Kermarrec 1fe7d09fb5 soc/integration/soc_core: add csr_map_update function 2018-11-21 08:39:52 +01:00
Tim Ansell ab799f7bd7
Merge pull request #127 from cr1901/picorv32-data
libbase/crt0-picorv32: Add support for .data sections.
2018-11-20 21:15:50 -08:00
William D. Jones 89c702187a libbase/crt0-picorv32: Add support for .data sections. 2018-11-21 00:13:13 -05:00
Florent Kermarrec 80bdae0e55 build/sim/verilator: add trace parameter to enable tracer 2018-11-20 18:54:22 +01:00
Florent Kermarrec 7359a99bf9 soc_core: convert cpu_type="None" string to None 2018-11-20 17:45:11 +01:00
Florent Kermarrec 5805d63013 build/microsemi/libero_soc: only associate timings constraint to timing check (otherwise we loose io constraints...), use default settings for place & route 2018-11-19 16:36:30 +01:00