Commit Graph

1644 Commits

Author SHA1 Message Date
Florent Kermarrec dfc207aacb litepcie: use data instead of dat in dma_layout (allow use of migen.actorlib.packet modules on dma dataflow) 2015-07-22 21:44:53 +02:00
Florent Kermarrec 40740d3ddc litepcie: use optional platform.misoc_path to add litepcie phy wrapper verilog files
We should eventually try to use python package_data or data_file for that.
2015-07-22 18:09:04 +02:00
Sebastien Bourdeauducq 84514cf8d5 uart: remove option to refill HW from uart_write 2015-07-19 23:41:38 +02:00
Robert Jordens a501d7c52d uart: support async phys 2015-07-19 23:37:00 +02:00
Robert Jordens 097248bce9 uart.c: rx overflow fix and tx simplification
* fixes the clearing of the rx ringbuffer on rx-overflow
* removes tx_level and tx_cts by restricting the ringbuffer
  to at least one slot empty
* agnostic of the details of the tx irq: works for uarts that
  generate tx interrupts on !tx-full or on tx-empty.
* only rx_produce and tx_consume need to be volatile
2015-07-19 23:37:00 +02:00
Florent Kermarrec 35250f5b11 bios: add romboot
When firmware is small enough, it can be interesting to run code from an embedded blockram memory (faster and not impacted by memory controller activity).
It can also be a fallback option in case boot from flash failed.
To use this, define ROM_BOOT_ADDRESS and initialize the blockram with the firmware data.
2015-07-14 18:01:44 +02:00
Florent Kermarrec 6c13879fb6 make.py: use sys.path.insert(0...) to allow external designs to have specific targets derived from a base target 2015-07-13 17:25:50 +02:00
Florent Kermarrec 4dca66b23d misoclib/video/dvisampler: add fifo_depth parameter 2015-07-13 11:03:33 +02:00
Florent Kermarrec e6da1d16b2 wishbone2lasmi: fix "READ_DATA" state 2015-07-09 10:40:32 +02:00
Florent Kermarrec d244eba583 tools/flterm.py: fix kernel-adr support 2015-07-07 14:58:49 +02:00
Florent Kermarrec 0545d49294 liteeth/core: add with_icmp parameter 2015-07-06 21:31:20 +02:00
Florent Kermarrec e011f9378f use sets for leave_out 2015-07-05 22:49:23 +02:00
Florent Kermarrec c100ef6406 liteeth/core/mac: adapt depth on AsyncFIFOs according to phy (reduce ressource usage with MII phy) 2015-07-05 22:45:53 +02:00
Florent Kermarrec c1ca928ec2 liteeth: small logic optimizations on mac (eases timings on spartan6) 2015-07-05 12:31:52 +02:00
Florent Kermarrec 23541b5949 software/bios: call eth_mode only if we have an ethernet mac (we don't need to call it when we have a hardware UDP/IP stack) 2015-07-04 21:04:23 +02:00
Yann Sionneau 10eb07526d bios: show memtest command in help 2015-07-02 17:20:06 +02:00
Sebastien Bourdeauducq 31a447154d soc: support constants without value 2015-06-28 21:35:37 +02:00
Sebastien Bourdeauducq e913fca8a0 libcompiler-rt: add fixdfdi 2015-06-27 23:51:09 +02:00
Joe Britton a1e3fb16ac flterm.py: use serial_for_url 2015-06-26 11:40:33 +02:00
Florent Kermarrec 04c64eb1d8 litesata/example_designs: fix core generation (RAID introduced some changes on the PHY) 2015-06-26 00:20:58 +02:00
enjoy-digital c615b50735 Merge pull request #14 from olofk/misc_fixes
Misc fixes
2015-06-25 23:59:42 +02:00
Olof Kindgren 52e6bf6987 litesata/test: Add missing dependency on scrambler in bist_tb 2015-06-26 01:20:25 +02:00
Olof Kindgren ffb6081720 litesata/example_designs: Add missing clock in phy instantiation 2015-06-26 01:20:25 +02:00
Florent Kermarrec 125432b5b6 liteeth/example_designs: use new Keep SynthesisDirective 2015-06-23 16:15:28 +02:00
Florent Kermarrec 351e654e9d software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache) 2015-06-23 09:01:34 +02:00
Robert Jordens 2150e6cfef pipistrello: run at 83+1/3 MHz, cleanup CRG 2015-06-22 18:56:57 -06:00
Florent Kermarrec 01c5051866 liteeth/software: fix wishbone bridge 2015-06-23 01:48:45 +02:00
Florent Kermarrec 369cf4c4d7 liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection 2015-06-23 01:08:49 +02:00
Florent Kermarrec 5c939b85ef liteeth/core/arp: fix table timer (wait_timer adaptation issue) 2015-06-23 00:25:26 +02:00
Florent Kermarrec a3c0e5c4d9 liteeth/core/arp: fix missing MAC address in ARP reply 2015-06-22 23:15:00 +02:00
Florent Kermarrec 781869d6f9 software/libbase/system: fix flush_l2_cache 2015-06-19 09:00:14 +02:00
Florent Kermarrec f44956bfca soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined 2015-06-19 08:39:37 +02:00
Sebastien Bourdeauducq 7c2d0fa641 indentation 2015-06-17 08:32:17 -06:00
Florent Kermarrec c0bc94ca1c soc/sdram: add capability to share L2 cache in multi-CPU SoCs 2015-06-17 15:48:45 +02:00
Florent Kermarrec 3b9f287bab sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon 2015-06-17 15:30:30 +02:00
Florent Kermarrec a1f7ecc8c5 litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :) 2015-06-10 12:15:59 +02:00
Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
2015-06-10 12:14:48 +02:00
Florent Kermarrec 1bb2580779 sdram: use new Migen Converter in Minicon frontend and small cleanup 2015-06-02 19:37:08 +02:00
Florent Kermarrec f96a856c97 sdram/phy: fix simphy memory usage 2015-06-02 19:33:09 +02:00
Florent Kermarrec f40140dba5 sdram: refactor minicon and fix issues with DDRx memories
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
2015-05-29 12:31:56 +02:00
Yann Sionneau a8b9c126cd spiflash: now using 64k sectors 2015-05-27 18:44:14 +08:00
Yann Sionneau 3f7e161867 spiflash: cleanup unnecessary parenthesis 2015-05-27 18:44:14 +08:00
Sebastien Bourdeauducq d50bb8c55e litesata: more doc fixes 2015-05-26 14:13:13 +08:00
Sebastien Bourdeauducq 1e47cfce2b Merge branch 'master' of https://github.com/m-labs/misoc
Conflicts:
	misoclib/mem/litesata/doc/source/docs/frontend/index.rst
2015-05-26 13:57:26 +08:00
Sebastien Bourdeauducq a9da892b57 litesata: doc fixes 2015-05-26 13:54:31 +08:00
Florent Kermarrec 989d8a7c29 liteata: fix spelling & mistakes in doc 2015-05-26 07:37:09 +02:00
Florent Kermarrec eb922f6ddc litesata: rework frontend doc and add striping, mirroring 2015-05-25 14:04:37 +02:00
Florent Kermarrec 0d1a7b9315 litesata: add mirroring 2015-05-25 14:03:14 +02:00
Florent Kermarrec c3716296ae litesata/examples_designs: add striping 2015-05-25 14:02:02 +02:00
Florent Kermarrec 0d2db23603 litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink) 2015-05-25 13:55:15 +02:00