Sebastien Bourdeauducq
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b862b070d6
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fhdl/verilog: recursive Special lowering
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2013-04-25 14:56:26 +02:00 |
Sebastien Bourdeauducq
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67c3119249
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genlib/fifo: add asynchronous FIFO
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2013-04-25 13:30:37 +02:00 |
Sebastien Bourdeauducq
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fee228a09f
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fhdl/specials/memory: do not write address register for async reads
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2013-04-25 13:30:05 +02:00 |
Sebastien Bourdeauducq
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6c08cd67aa
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graycounter: expose binary output
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2013-04-25 13:11:15 +02:00 |
Sebastien Bourdeauducq
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0f9df2d732
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genlib: add Gray counter
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2013-04-24 19:13:36 +02:00 |
Florent Kermarrec
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f599fe4ade
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Support for resetless clock domains
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2013-04-23 11:54:05 +02:00 |
Sebastien Bourdeauducq
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ceb0a99d83
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Change license to 2-clause BSD
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2013-04-15 23:55:30 +02:00 |
Sebastien Bourdeauducq
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8e11fcf1d0
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bus/csr/SRAM: fix Module conversion errors
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2013-04-14 13:55:04 +02:00 |
Sebastien Bourdeauducq
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ea63389823
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fhdl: support len() on all values
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2013-04-14 13:50:26 +02:00 |
Sebastien Bourdeauducq
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75d33a0c05
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fhdl/verilog/_printinit: initialize undriven Special inputs (bug reported by Florent Kermarrec)
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2013-04-11 18:55:49 +02:00 |
Sebastien Bourdeauducq
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72ef4b9683
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ioo+pytholite: use new Module API
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2013-04-10 23:42:46 +02:00 |
Sebastien Bourdeauducq
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4c9018ea17
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fhdl/visit: add TransformModule
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2013-04-10 23:42:14 +02:00 |
Sebastien Bourdeauducq
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746acdacd1
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ioo: move to genlib
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2013-04-10 22:28:53 +02:00 |
Sebastien Bourdeauducq
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1cc4c8ee9f
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uio: remove Trampoline (Python 3.3 provides generator delegation instead)
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2013-04-10 22:15:28 +02:00 |
Sebastien Bourdeauducq
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6ce856290a
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flow: match record fields by position
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2013-04-10 21:33:56 +02:00 |
Sebastien Bourdeauducq
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df1ed32765
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genlib/record/connect: add match_by_position
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2013-04-10 21:33:45 +02:00 |
Sebastien Bourdeauducq
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692794a21f
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flow: use Module and new Record APIs
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2013-04-10 19:12:42 +02:00 |
Sebastien Bourdeauducq
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20bdd424c8
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flow: adapt to new Record API
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2013-04-01 22:15:23 +02:00 |
Sebastien Bourdeauducq
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29b468529f
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bus: replace simple bus module with new bidirectional Record
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2013-04-01 21:54:21 +02:00 |
Sebastien Bourdeauducq
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6a3c413717
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New bidirectional-capable Record API
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2013-04-01 21:53:33 +02:00 |
Sebastien Bourdeauducq
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c4f4143591
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New CSR API
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2013-03-30 17:28:41 +01:00 |
Sebastien Bourdeauducq
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633e5e6747
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fhdl/module/finalize: pass additional args to do_finalize
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2013-03-30 11:29:46 +01:00 |
Sebastien Bourdeauducq
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574becc1fc
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fhdl/specials: clean up clock domain handling
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2013-03-26 11:58:34 +01:00 |
Sebastien Bourdeauducq
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77a0f0a3bb
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actorlib/structuring/Cast: support inversion
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2013-03-25 15:54:09 +01:00 |
Sebastien Bourdeauducq
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c4c4765a4e
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bank/csrgen/BankArray: retain name information
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2013-03-25 14:44:15 +01:00 |
Sebastien Bourdeauducq
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53edc3557e
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bank/description/Register: add get_size
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2013-03-25 14:43:44 +01:00 |
Sebastien Bourdeauducq
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3da98ea04d
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genlib/record: use getattr instead of __dict__
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2013-03-24 00:51:01 +01:00 |
Sebastien Bourdeauducq
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1897b74f97
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genlib/record: add eq
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2013-03-24 00:50:33 +01:00 |
Sebastien Bourdeauducq
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9d7c679b8c
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genlib/fifo: simple synchronous FIFO
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2013-03-22 18:18:38 +01:00 |
Sebastien Bourdeauducq
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ca431fc7c2
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fhdl/module: support clock domain remapping of submodules
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2013-03-22 18:17:54 +01:00 |
Sebastien Bourdeauducq
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a94bf3b2c5
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genlib/cdc/MultiReg: output clock domain defaults to sys
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2013-03-21 10:40:02 +01:00 |
Sebastien Bourdeauducq
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b38818eb17
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examples/sim/fir: convert to new API
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2013-03-19 11:46:27 +01:00 |
Sebastien Bourdeauducq
|
17f2b17654
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fhdl/verilog: optionally disable clock domain creation
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2013-03-18 18:45:19 +01:00 |
Sebastien Bourdeauducq
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af4eb02551
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examples/basic/arrays: demonstrate lowering of Array in Instance expression
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2013-03-18 18:37:23 +01:00 |
Sebastien Bourdeauducq
|
7a06e9457c
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Lowering of Special expressions + support ClockSignal/ResetSignal
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2013-03-18 18:36:50 +01:00 |
Sebastien Bourdeauducq
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dc55289323
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fhdl/tools/_ArrayLowerer: complete support for arrays as targets
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2013-03-18 14:38:01 +01:00 |
Sebastien Bourdeauducq
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e95d2f4779
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fhdl/tools/value_bits_sign: support not
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2013-03-18 09:52:43 +01:00 |
Sebastien Bourdeauducq
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b6fe3ace05
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fhdl/structure: style fix
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2013-03-17 15:33:38 +01:00 |
Sébastien Bourdeauducq
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2a4cc3875c
|
Merge pull request #6 from larsclausen/master
Minor improvements
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2013-03-17 07:33:14 -07:00 |
Sebastien Bourdeauducq
|
2f522bdd9f
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genlib/cdc/MultiReg: implement rename_clock_domain + get_clock_domains
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2013-03-15 19:50:24 +01:00 |
Sebastien Bourdeauducq
|
e2d156ef64
|
genlib/cdc/MultiReg: remove idomain
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2013-03-15 19:49:24 +01:00 |
Sebastien Bourdeauducq
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7b49fd9386
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fhdl/specials: fix rename_clock_domain declarations
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2013-03-15 19:47:01 +01:00 |
Sebastien Bourdeauducq
|
51bec340ab
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sim: remove PureSimulable (superseded by Module)
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2013-03-15 19:41:30 +01:00 |
Sebastien Bourdeauducq
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dd0f3311cd
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structure: remove Fragment.call_sim
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2013-03-15 19:15:48 +01:00 |
Sebastien Bourdeauducq
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9b9bd77d00
|
sim: compatibility with new ClockDomain API
|
2013-03-15 19:15:28 +01:00 |
Sebastien Bourdeauducq
|
208e039bbb
|
Local clock domain example
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2013-03-15 18:18:32 +01:00 |
Sebastien Bourdeauducq
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bd8bbd9305
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Make ClockDomains part of fragments
|
2013-03-15 18:17:33 +01:00 |
Sebastien Bourdeauducq
|
5adab17efa
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flow/actor/filter_endpoints: deterministic order
|
2013-03-14 12:20:18 +01:00 |
Sebastien Bourdeauducq
|
fc883198ae
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bank/csrgen/BankArray: create banks in sorted order
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2013-03-13 23:07:44 +01:00 |
Sebastien Bourdeauducq
|
52d13959f2
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bank/description: modify reg/mem in-place
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2013-03-13 19:46:34 +01:00 |