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9679 Commits

Author SHA1 Message Date
Sebastien Bourdeauducq e913fca8a0 libcompiler-rt: add fixdfdi 2015-06-27 23:51:09 +02:00
Joe Britton a1e3fb16ac flterm.py: use serial_for_url 2015-06-26 11:40:33 +02:00
Florent Kermarrec 04c64eb1d8 litesata/example_designs: fix core generation (RAID introduced some changes on the PHY) 2015-06-26 00:20:58 +02:00
enjoy-digital c615b50735 Merge pull request #14 from olofk/misc_fixes 
Misc fixes
 2015-06-25 23:59:42 +02:00
Olof Kindgren 52e6bf6987 litesata/test: Add missing dependency on scrambler in bist_tb 2015-06-26 01:20:25 +02:00
Olof Kindgren ffb6081720 litesata/example_designs: Add missing clock in phy instantiation 2015-06-26 01:20:25 +02:00
Sébastien Bourdeauducq f03c2325d9 Merge pull request #21 from psmears/patch-1 
Minor improvements to wording
 2015-06-24 10:46:58 +00:00
Florent Kermarrec 125432b5b6 liteeth/example_designs: use new Keep SynthesisDirective 2015-06-23 16:15:28 +02:00
Florent Kermarrec d77a5fc5ac fhdl/specials: add Keep SynthesisDirective 2015-06-23 16:14:42 +02:00
Florent Kermarrec 351e654e9d software/bios/sdram: flush dcache and l2 in memtest (otherwise we are partially testing the cache) 2015-06-23 09:01:34 +02:00
Robert Jordens 2150e6cfef pipistrello: run at 83+1/3 MHz, cleanup CRG 2015-06-22 18:56:57 -06:00
Florent Kermarrec 01c5051866 liteeth/software: fix wishbone bridge 2015-06-23 01:48:45 +02:00
Florent Kermarrec 369cf4c4d7 liteeth/example_designs: add false path between clock domains (speed up implementation) and use automatic PHY detection 2015-06-23 01:08:49 +02:00
Florent Kermarrec 5c939b85ef liteeth/core/arp: fix table timer (wait_timer adaptation issue) 2015-06-23 00:25:26 +02:00
Florent Kermarrec a3c0e5c4d9 liteeth/core/arp: fix missing MAC address in ARP reply 2015-06-22 23:15:00 +02:00
Florent Kermarrec 781869d6f9 software/libbase/system: fix flush_l2_cache 2015-06-19 09:00:14 +02:00
Florent Kermarrec f44956bfca soc/sdram: add L2_SIZE constant and avoid declaring an empty flush_l2_cache function when L2_SIZE is not defined 2015-06-19 08:39:37 +02:00
Florent Kermarrec 71627cf9f0 bus/wishbone: remove size CSR from Cache (L2 size will be reported to the software as a constant) 2015-06-19 08:37:16 +02:00
Florent Kermarrec 7d8f4d1009 mibuild/xilinx/ise: fix source and set source to False by default on Windows (tools supposed to be in the PATH) 2015-06-19 00:52:39 +02:00
Florent Kermarrec 743a5f6ea9 mibuild/xilinx/ise: simplify default_ise_path 2015-06-19 00:40:05 +02:00
William D. Jones 6370acd968 Xilinx Platforms now use cmd.exe on Windows instead of bash to run scripts 
(remove MSYS dependency)
 2015-06-19 00:30:22 +02:00
psmears d435f30fa3 Minor improvements to wording 2015-06-18 12:26:22 +01:00
Sebastien Bourdeauducq 7c2d0fa641 indentation 2015-06-17 08:32:17 -06:00
Florent Kermarrec c0bc94ca1c soc/sdram: add capability to share L2 cache in multi-CPU SoCs 2015-06-17 15:48:45 +02:00
Florent Kermarrec f8b1152b98 wishbone: add Cache (from WB2LASMI) 2015-06-17 15:31:49 +02:00
Florent Kermarrec 3b9f287bab sdram: use wishbone cache as L2 cache and add optional L2 cache to Minicon 2015-06-17 15:30:30 +02:00
Yann Sionneau 6e876c63ad pipistrello: fix FPGA speed grade 2015-06-14 23:19:27 +02:00
Florent Kermarrec a1f7ecc8c5 litesata: use 200MHz clock and SATA3 (6.0Gb/s) on all example designs: working :) 2015-06-10 12:15:59 +02:00
Florent Kermarrec 571ce5791a litesata/phy/k7: apply AR# 63869 to keep CDR in hold during SATA link initialization 
self.rxelecidle is already filtered so the "20 USRCLK cycles before setting RXCDRHOLD to 1'b0" are respected.
 2015-06-10 12:14:48 +02:00
Florent Kermarrec 1bb2580779 sdram: use new Migen Converter in Minicon frontend and small cleanup 2015-06-02 19:37:08 +02:00
Florent Kermarrec f96a856c97 sdram/phy: fix simphy memory usage 2015-06-02 19:33:09 +02:00
Florent Kermarrec 33b536e505 migen/bus/wishbone: add UpConverter and Converter wrapper (also rewrite DownConverter) 2015-06-02 19:29:38 +02:00
Florent Kermarrec 79624ce849 migen/genlib/fsm: fix delayed_enter when delay is negative (can happen when delay is generated from others parameters) 2015-06-02 19:26:42 +02:00
Sebastien Bourdeauducq fd16b66bdf genlib/cdc: add BusSynchronizer 2015-06-02 17:40:42 +08:00
Florent Kermarrec f40140dba5 sdram: refactor minicon and fix issues with DDRx memories 
- simplify code
- fix AddressSlicer
- manage write latency and write to precharge timings
- add odt/reset_n signals
 2015-05-29 12:31:56 +02:00
Sebastien Bourdeauducq 57102ec160 setup.py: valid version number (fixes issue #12) 2015-05-28 15:43:31 +08:00
Yann Sionneau a8b9c126cd spiflash: now using 64k sectors 2015-05-27 18:44:14 +08:00
Yann Sionneau 3f7e161867 spiflash: cleanup unnecessary parenthesis 2015-05-27 18:44:14 +08:00
Sebastien Bourdeauducq d50bb8c55e litesata: more doc fixes 2015-05-26 14:13:13 +08:00
Sebastien Bourdeauducq 1e47cfce2b Merge branch 'master' of https://github.com/m-labs/misoc 
Conflicts:
	misoclib/mem/litesata/doc/source/docs/frontend/index.rst
 2015-05-26 13:57:26 +08:00
Sebastien Bourdeauducq a9da892b57 litesata: doc fixes 2015-05-26 13:54:31 +08:00
Florent Kermarrec 989d8a7c29 liteata: fix spelling & mistakes in doc 2015-05-26 07:37:09 +02:00
Florent Kermarrec eb922f6ddc litesata: rework frontend doc and add striping, mirroring 2015-05-25 14:04:37 +02:00
Florent Kermarrec 0d1a7b9315 litesata: add mirroring 2015-05-25 14:03:14 +02:00
Florent Kermarrec c3716296ae litesata/examples_designs: add striping 2015-05-25 14:02:02 +02:00
Florent Kermarrec 0d2db23603 litesata/core/link: move buffer on CONTInserter (seems better for timings when set on sink) 2015-05-25 13:55:15 +02:00
Florent Kermarrec cb053dc011 liteusb/core/packet: fix missing , 2015-05-25 13:53:02 +02:00
Florent Kermarrec 1bb5a05488 litesata: add striping module for use of multiple HDDs. 2015-05-23 14:12:20 +02:00
Florent Kermarrec 5daba9af68 litesata: do some cleanup and prepare for RAID 2015-05-23 14:08:56 +02:00
Florent Kermarrec a5f495aeac fhdl/verilog: add reserved keywords 2015-05-23 14:01:08 +02:00