Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity
6915 commits 42 branches 14 tags 31 MiB
Commit graph

6915 commits

This branch
This branch
All branches
Author SHA1 Message Date
Evan Lojewski
08072eb872 xics: Disable endianness swapping 
The endianess swapping code caused the core to diverge from microwatt resulting in:
- The xics tests not working as-is: https://github.com/antonblanchard/microwatt/blob/master/tests/xics/xics.h
- byte writes writing to the incorrect byte

This removes endianswapping and minimizes the delta from upstream for the xics irq.h header.
 2021-03-10 07:39:19 -07:00
Evan Lojewski
c92e4cb3ca xics: Ass missing static keywords to irq header. 2021-03-10 07:32:24 -07:00
Florent Kermarrec
9d08c65e8a build/generic_platform: Make sure default_clk_period constraint is only applied when default_clk_period exists. 
In simulation, default_clk_period is not necessarily required.
 2021-03-10 12:25:35 +01:00
enjoy-digital
ee2d373477
Merge pull request #843 from gregdavill/monitor_token_fix 
cores/stream/monitor: Fix typo
 2021-03-10 11:00:55 +01:00
Florent Kermarrec
e48b269d77 build/generic_platform: Fix use_default_clk set when not user provided sys_clk. 
Prevented the default timing constraint to be generated in the timing constraint file.
 2021-03-10 10:47:22 +01:00
Greg Davill
31cc7f1e42 cores/stream/monitor: Fix typo 2021-03-10 09:11:07 +10:30
Florent Kermarrec
0e7d8219ea soc/cores/gpio: Simplify GPIOIn IRQ, make polarity configurable and also add optional IRQ to GPIOTristate. 
Ex of instance:
from litex.soc.cores import gpio
gpio_in_pads = Signal(16)
self.submodules.gpio_in = gpio.GPIOIn(gpio_in_pads, with_irq=True)
self.add_csr("gpio_in")
 2021-03-09 13:57:48 +01:00
Florent Kermarrec
0d8b6f8fbb csr_eventmanager/EventSourceProcess: Add Rising Edge support and Falling/Rising selection. 2021-03-09 13:55:43 +01:00
Florent Kermarrec
ece9005949 cpu/vexriscv/core: Rename timer_enabled parameter to with_timer (for consistency with codebase) and disable timer by default (since increasing resources and causing issue on some iCE40 designs). 2021-03-09 09:07:52 +01:00
enjoy-digital
834c90b71f
Merge pull request #841 from gatecat/radiant_pins_x 
build/radiant: Skip location constraint for X pins
 2021-03-08 16:30:22 +01:00
gatecat
c64e2d3a85 build/radiant: Skip location constraint for X pins 
Signed-off-by: gatecat <gatecat@ds0.me>
 2021-03-08 14:27:32 +00:00
Florent Kermarrec
5af8e5c934 soc/add_etherbone: Fix UDPIPCore clock domain (should still run at eth_clk even if Etherbone is running in sys_clk) since data-width convertion is done on UDP. 2021-03-08 13:50:22 +01:00
Vamsi Vytla
6bb0541f9a Remove ussysmon.py as it is consolidated inside xadc.py 2021-03-06 14:31:24 -08:00
Florent Kermarrec
a1e54671be sim/serial2console: Remove \r workaround since no longer required and generating double carrier return in simulation. 2021-03-06 17:36:21 +01:00
Florent Kermarrec
7e3912aaef software/demo: Make hellocpp optional (only build with --with-cxx) to avoid adding g++ as a dependency for an optional feature. 2021-03-06 17:31:07 +01:00
Vamsi Vytla
647d3eb51a soc/cores/xadc.py: Move ussysmon here 2021-03-06 08:14:13 -08:00
Florent Kermarrec
31ac6659c9 cores/video: Add VideoS7HDMIPHY for Xilinx 7-Series. 2021-03-05 14:30:28 +01:00
Florent Kermarrec
9624cce188 cores/video: Mode VideoVGAPHY/VideoDVIPHY and add separators. 2021-03-05 14:27:08 +01:00
Florent Kermarrec
0280a9dd57 soc/add_video_framebuffer: Pass clock_domain to VideoFrameBuffer. 2021-03-05 14:23:39 +01:00
Florent Kermarrec
8b531b4215 cores: Add code_tmds with TMDS Encoder from Mixxeo/LiteVideo. 2021-03-04 19:32:41 +01:00
Florent Kermarrec
10d87e4138 cores/video/VideoPHYs: Use IO primitives. 2021-03-04 18:22:34 +01:00
Florent Kermarrec
82d0ecd7bd cores/video/VideoTerminal: Add CLEAR-XY after reset. 2021-03-04 17:55:37 +01:00
Florent Kermarrec
a1e7aab35c cores/clock/xilinx_usp/USPIDELAYCTRL: Apply USIDELAYCTRL's changes. 2021-03-04 14:42:50 +01:00
Florent Kermarrec
60e2d3335f cores/clock/xilinx_us: Remove USP modules (refactoring issue). 2021-03-04 14:42:03 +01:00
Florent Kermarrec
2d5b4b206b bios: Add VideoFrameBuffer VTG/DMA initialisation. 
This just configures the enables for now since other parameters are pre-configured
during the build.
 2021-03-04 12:01:32 +01:00
Florent Kermarrec
f553b5fc83 soc/cores/video: Improve/Cleanup VideoFrameBuffer, disable by default and modify default hres/vres to 800/600. 2021-03-04 11:59:44 +01:00
Florent Kermarrec
0ee92448b9 soc/cores/dma: Add default parameters to add_csr (similar to LiteDRAMDMAs), minor cosmetic cleanups and also add offset CSRStatus on WishboneDMAWriter (for symetry with WishboneDMAReader). 
Defaults parameters can allow the FPGA gateware to behave by itself after initialization while still being configurable by software.
 2021-03-04 11:53:43 +01:00
Florent Kermarrec
225a518f7e soc/cores/video: Move LiteDRAMDMAReader import to VideoFramerBuffer to avoid LiteDRAM dependency. 2021-03-04 08:40:47 +01:00
Vamsi Vytla
ae5f67f6f0 litex/soc/cores/ussysmon.py: minor bug 2021-03-03 14:47:52 -08:00
Vamsi Vytla
1793efb50b litex/soc/cores/ussysmon.py: dadr address space bump 2021-03-03 14:38:27 -08:00
Florent Kermarrec
ccc8916995 soc/cores/video: Add initial (and simple) VideoFrameBuffer core. 2021-03-03 19:58:11 +01:00
Vamsi Vytla
922f85e64b litex/soc/cores/ussysmon.py: ADC transfer function 2021-03-03 10:50:58 -08:00
Florent Kermarrec
24fb153fa1 soc/integration: Add add_video_terminal method to LiteXSoC. 
Adds the new LiteX's VideoTerminal core to the SoC:

self.submodules.videophy = VideoVGAPHY(platform.request("vga"), clock_domain="vga")
self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="vga")
 2021-03-03 17:45:02 +01:00
Florent Kermarrec
35ffba8801 soc/cores: Add simple VideoOut core with VideoTimingGenerator, Video Patterns, VideoTerminal, VideoDVIPHY and VideoVGAPHY. 2021-03-03 16:17:12 +01:00
Florent Kermarrec
c5ee6741a0 software/liblitedram: Use new DQS delay reset procedure on Ultrascale(+) (by increments). 2021-03-03 11:32:43 +01:00
Florent Kermarrec
d3407c67b1 build/sim/core: Cast main_time to vluint64_t to avoid ambiguity error of the dump function to be used. 2021-03-03 09:25:54 +01:00
Florent Kermarrec
134c628357 cores/spi_flash: Minor cosmetic cleanups, SpiFlashQuadReadWrite has also been moved to the end with a Note since should probably be re-factored. 2021-03-03 09:15:51 +01:00
Florent Kermarrec
61dcd1e8fd soc/cores/led: Minor cosmetic cleanups. 2021-03-03 09:02:41 +01:00
Florent Kermarrec
19b1e50cbd soc/cores/icap: Minor cosmetic cleanups. 2021-03-03 09:01:41 +01:00
Florent Kermarrec
e6f1d677e7 soc/cores/freqmeter: Minor cosmetic cleanups. 2021-03-03 08:59:51 +01:00
Florent Kermarrec
ce5e3e3b93 soc/cores/ecc: Minor cosmetic cleanups. 2021-03-03 08:55:37 +01:00
Florent Kermarrec
2fd7451fc9 soc/cores/code_8b10b: Minor cosmetic cleanups. 2021-03-03 08:54:31 +01:00
Florent Kermarrec
2e531e0ec7 soc/cores/dna: Add separator/comment. 2021-03-03 08:49:47 +01:00
Vamsi Vytla
71f7ce6a57 soc/cores/ussysmon.py: Xilinx XADC like thingy for UltraScale devices 2021-03-02 20:31:52 -08:00
enjoy-digital
c23e8813fc
Merge pull request #836 from hplp/master 
demo with c++ HW example
 2021-03-02 09:13:10 +01:00
Sergiu Mosanu
7fd39235af
Merge pull request #1 from hplp/cppdemo 
demo with basic C and C++ examples
 2021-03-02 01:31:46 -05:00
Sergiu Mosanu
769f36d468 extend demo with basic C and C++ examples 2021-03-02 01:28:21 -05:00
enjoy-digital
415bf63594
Merge pull request #830 from dayjaby/vexriscv_mem_map 
VexRiscv: More general mem_map
 2021-03-01 11:15:56 +01:00
David Jablonski
ceb8a6502c VexRiscv: More general mem_map 2021-02-25 10:36:43 +01:00
Florent Kermarrec
6e883b4513 tools/litex_sim: Add boot to main_ram when sdram_init contents provided. 2021-02-25 09:10:26 +01:00