Sebastien Bourdeauducq
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b7a84b3750
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wishbone: base TargetModel class
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2012-06-10 17:05:10 +02:00 |
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Sebastien Bourdeauducq
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ec501e7797
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bus/wishbone: target model
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2012-06-10 16:40:33 +02:00 |
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Sebastien Bourdeauducq
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5964df62db
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examples/dataflow: only import nx when needed
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2012-06-08 22:54:04 +02:00 |
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Sebastien Bourdeauducq
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009f26bb9d
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flow/network: refactor graph
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2012-06-08 22:49:49 +02:00 |
|
Sebastien Bourdeauducq
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f86170e349
|
actorlib: WB writer simulation OK
|
2012-06-08 21:31:57 +02:00 |
|
Sebastien Bourdeauducq
|
356051e8a8
|
actorlib: WB reader simulation OK
|
2012-06-08 21:31:05 +02:00 |
|
Sebastien Bourdeauducq
|
910c7806cf
|
actorlib: generator-based generic simulation actor
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2012-06-08 17:54:03 +02:00 |
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Sebastien Bourdeauducq
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d280723618
|
examples/fir: print Verilog source
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2012-06-08 14:00:49 +02:00 |
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Sebastien Bourdeauducq
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b00e8fa826
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examples/fir: plot input and output signals
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2012-06-07 23:20:59 +02:00 |
|
Sebastien Bourdeauducq
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081b658e2d
|
Update copyright notices
|
2012-03-23 16:41:30 +01:00 |
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Sebastien Bourdeauducq
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f6e76ae198
|
doc: more examples and comments
|
2012-03-10 19:38:39 +01:00 |
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Sebastien Bourdeauducq
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57a87b3316
|
examples: FIR filter simulation
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2012-03-08 20:49:36 +01:00 |
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Sebastien Bourdeauducq
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f4adb0fe9c
|
examples: remove outdated wb_intercon simulation
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2012-03-08 18:17:56 +01:00 |
|
Sebastien Bourdeauducq
|
ab800fa2ed
|
bus: generic transaction model
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2012-03-08 18:14:06 +01:00 |
|
Sebastien Bourdeauducq
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59a57e7a76
|
examples: small cleanup
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2012-03-08 15:55:02 +01:00 |
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Sebastien Bourdeauducq
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98e96b3952
|
sim: make initialization cycle optional (selectable by function attribute)
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2012-03-06 19:43:59 +01:00 |
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Sebastien Bourdeauducq
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8160ced2e9
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sim: memory access
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2012-03-06 19:29:39 +01:00 |
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Sebastien Bourdeauducq
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6f829c7afc
|
sim: support for signed numbers
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2012-03-06 16:46:18 +01:00 |
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Sebastien Bourdeauducq
|
9da512dbf5
|
sim: VCD generation
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2012-03-06 15:26:04 +01:00 |
|
Sebastien Bourdeauducq
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22b3c11b93
|
sim: clean startup/shutdown
|
2012-03-06 15:00:02 +01:00 |
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Sebastien Bourdeauducq
|
aac9752558
|
sim: basic functionality working
|
2012-03-05 20:31:41 +01:00 |
|
Sebastien Bourdeauducq
|
ca7056b07f
|
fhdl: support forwarding of bidirectional signals from instance ports
|
2012-02-16 18:34:32 +01:00 |
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Sebastien Bourdeauducq
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ef7aea0f31
|
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
|
2012-02-15 18:23:31 +01:00 |
|
Sebastien Bourdeauducq
|
91e279ee04
|
bank/csrgen: use new bus API
|
2012-02-15 16:42:17 +01:00 |
|
Sebastien Bourdeauducq
|
0493212124
|
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
|
2012-02-15 16:30:16 +01:00 |
|
Sebastien Bourdeauducq
|
0c214b484e
|
Use double quotes for all strings
|
2012-02-14 13:12:43 +01:00 |
|
Sebastien Bourdeauducq
|
3a2a0c4dd8
|
bank: support registers larger than the bus word width
|
2012-02-06 16:15:27 +01:00 |
|
Sebastien Bourdeauducq
|
f3ddfffc47
|
bank: refactoring
|
2012-02-06 13:55:50 +01:00 |
|
Sebastien Bourdeauducq
|
3143608e0a
|
examples/wb_intercon: update to new APIs
|
2012-01-28 23:18:21 +01:00 |
|
Sebastien Bourdeauducq
|
685b5eb08f
|
fhdl: support memory read enable
|
2012-01-27 21:39:23 +01:00 |
|
Sebastien Bourdeauducq
|
5405a83ff9
|
fhdl: memories working
|
2012-01-27 20:22:17 +01:00 |
|
Sebastien Bourdeauducq
|
076c171c7b
|
Use meaningful class names
|
2012-01-20 23:07:32 +01:00 |
|
Sebastien Bourdeauducq
|
a1043d11c0
|
examples/corelogic_conv: use two dividers
|
2012-01-16 19:38:39 +01:00 |
|
Sebastien Bourdeauducq
|
bdde97f5fd
|
New naming system beginning to work
|
2012-01-16 18:42:55 +01:00 |
|
Sebastien Bourdeauducq
|
e6bfad498d
|
actorlib/control: 'for' generator
|
2012-01-15 22:08:33 +01:00 |
|
Sebastien Bourdeauducq
|
85491efc68
|
wishbone_dma: convert to new endpoint API and fix some bugs
|
2012-01-15 16:41:15 +01:00 |
|
Sebastien Bourdeauducq
|
a6e5f3e766
|
flow: simplify actor fragment interface
|
2012-01-10 15:54:51 +01:00 |
|
Sebastien Bourdeauducq
|
683e6b4a6c
|
record: support aligned flattening
|
2012-01-09 19:16:11 +01:00 |
|
Sebastien Bourdeauducq
|
b06e70d849
|
corelogic: FSM
|
2012-01-09 16:28:48 +01:00 |
|
Sebastien Bourdeauducq
|
89bf704b2b
|
record: preserve order
|
2012-01-09 15:14:42 +01:00 |
|
Sebastien Bourdeauducq
|
bdcaeb159b
|
flow: draw network graph
|
2012-01-09 14:21:54 +01:00 |
|
Sebastien Bourdeauducq
|
d2d55372d8
|
Composer (WIP)
|
2012-01-08 13:56:11 +01:00 |
|
Sebastien Bourdeauducq
|
0b195a244d
|
flow: network
|
2012-01-07 00:33:28 +01:00 |
|
Sebastien Bourdeauducq
|
588f1a259e
|
flow: plumbing
|
2012-01-06 17:24:05 +01:00 |
|
Sebastien Bourdeauducq
|
038992e7d2
|
corelogic: record
|
2012-01-06 11:20:44 +01:00 |
|
Sebastien Bourdeauducq
|
9366a226bb
|
Convert -> convert
|
2012-01-05 19:27:33 +01:00 |
|
Sebastien Bourdeauducq
|
1ce4fbdb98
|
example: flow conversion
|
2011-12-23 00:36:07 +01:00 |
|
Sebastien Bourdeauducq
|
af0a03b65f
|
examples: remove old-style declarations
|
2011-12-18 21:54:39 +01:00 |
|
Sebastien Bourdeauducq
|
39b7190334
|
Pay a bit more attention to PEP8
|
2011-12-16 16:02:55 +01:00 |
|
Sebastien Bourdeauducq
|
6f7a35e0a3
|
examples: Wishbone interconnect test bench
|
2011-12-13 14:10:56 +01:00 |
|
Sebastien Bourdeauducq
|
5034af3038
|
Corelogic conversion example
|
2011-12-08 21:25:05 +01:00 |
|
Sebastien Bourdeauducq
|
1b637cea61
|
Instance support
|
2011-12-08 16:35:32 +01:00 |
|
Sebastien Bourdeauducq
|
ec51f09c98
|
Case support + register bank generator
|
2011-12-05 17:43:56 +01:00 |
|
Sebastien Bourdeauducq
|
5acf2e169f
|
Examples folder
|
2011-12-04 23:39:48 +01:00 |